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54FCT841ADB

Part # 54FCT841ADB
Description
Category IC
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Qty 48
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Integrated Device Technology
Date Code: 9220
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1994
1994 Integrated Device Technology, Inc. 7.22 DSC-4603/2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
FEATURES:
Equivalent to AMD’s Am29841-46 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
IDT54/74FCT841A equivalent to FAST speed
IDT54/74FCT841B 25% faster than FAST
IDT54/74FCT841C 40% faster than FAST
Buffered common latch enable, clear and preset inputs
•I
OL = 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 10-bit wide version of the popular ‘373 function.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-imped-
ance state.
1
2607 drw 01
FUNCTIONAL BLOCK DIAGRAM
D0
D
CLR
Y
0
LE
Q
P
CLR
LE
OE
PRE
DN
D
CLR
Y
N
LE
Q
P
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
7.22 2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
D
0
D1
D2
D3
D4
D5
D6
D7
GND
Y
0
Y1
Y2
Y3
Y4
Y6
LE
Y
5
Y7
VCC
P24-1
D24-1
E24-1
&
SO24-2
D
8
D9
Y8
Y9
DIP/CERPACK/SOIC
TOP VIEW
INDEX
D2
Y2
Y3
Y4
NC
Y
5
OE
D
1
NC
V
CC
Y0
D8
GND
LE
Y
9
Y8
LCC
TOP VIEW
L28-1
D3
D4
NC
D
5
D6
D7
D0
Y1
Y6
Y7
D9
NC
32
20
19
1
4
5
6
7
8
1817161514
9
10
11
12 13
21
22
23
24
25
262728
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
11
12
21
22
23
24
2607 drw 02
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE
(1)
Name I/O Description
I When is LOW, the outputs are
LOW if is LOW. When is HIGH,
data can be entered into the latch.
DI I The latch data inputs.
LE I The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
YI O The 3-state latch outputs.
I The output enable control. When is
LOW, the outputs are enabled. When
is HIGH, the outputs (Y
I) are in the
high-impedance (off) state.
I Preset line. When is LOW, the
outputs are HIGH if is LOW. Preset
overrides .
2607 tbl 01
Inputs
Inter-
nal
Out-
puts
LE D
I
Q
I
Y
I
Function
H H H X X X Z High Z
H H H H L L Z High Z
H H H H H H Z High Z
H H H L X NC Z Latched (High Z)
H H L H L L L Transparent
H H L H H H H Transparent
H H L L X NC NC Latched
H L L X X H H Preset
L H L X X L L Clear
L L L X X H H Preset
L H H L X L Z Latched (High Z)
H L H L X H Z Latched (High Z)
NOTE: 2607 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
Z = High Impedance
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22 3
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
VTERM
(2)
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM
(3)
Terminal Voltage
with Respect to
GND
–0.5 to VCC –0.5 to VCC V
TA Operating
Temperature
0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias
–55 to +125 –65 to +135 °C
TSTG Storage
Temperature
–55 to +125 –65 to +150 °C
PT Power Dissipation 0.5 0.5 W
IOUT DC Output
Current
120 120 mA
NOTE: 2607 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC by +0.5V unless otherwise noted.
2. Input and V
CC terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Typ. Max. Unit
C
IN
Input
Capacitance
V
IN
= 0V 6 10 pF
C
OUT
Output
Capacitance
V
OUT
= 0V 8 12 pF
NOTE: 2607 tbl 04
1. This parameter is measured at characterization but not tested.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC
= 5.0V ± 10%
NOTES: 2607 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 V
VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC —— 5µA
VI = 2.7V 5
(4)
II L Input LOW Current VI = 0.5V –5
(4)
VI = GND –5
IOZH Off State (High Impedance) VCC = Max. VO = VCC ——10µA
Output Current VO = 2.7V 10
(4)
IOZL VO = 0.5V –10
(4)
VO = GND –10
VIK Clamp Diode Voltage VCC = Min., IN = –18mA –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
(3)
, VO = GND –75 –120 mA
VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V
VCC = Min. IOH = –300µAVHC VCC
VIN = VIH or VIL IOH = –15mA MIL. 2.4 4.3
IOH = –24mA COM'L. 2.4 4.3
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA GND VLC V
VCC = Min. IOL = 300µA GND VLC
(4)
VIN = VIH or VIL IOL = 32mA MIL. 0.3 0.5
IOL = 48mA COM'L. 0.3 0.5
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