Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992

1992 Integrated Device Technology, Inc. 7.10 DSC-4609/2



IDT54/74FCT273

IDT54/74FCT273A

IDT54/74FCT273C

FAST CMOS

OCTAL FLIP-FLOP

WITH MASTER RESET

FEATURES:

• IDT54/74FCT273 equivalent to FAST speed;

• IDT54/74FCT273A 45% faster than FAST

• IDT54/74FCT273C 55% faster than FAST

• Equivalent to FAST output drive over full temperature

and voltage supply extremes

•IOL = 48mA (commercial) and 32mA (military)

• CMOS power levels (1mW typ. static)

• TTL input and output level compatible

• CMOS output level compatible

• Substantially lower input current levels than FAST

(5µA max.)

• Octal D flip-flop with Master Reset

• JEDEC standard pinout for DIP and LCC

• Product available in Radiation Tolerant and Radiation

Enhanced versions

• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT54/74FCT273/A/C are octal D flip-flops built using

an advanced dual metal CMOS technology. The IDT54/

74FCT273/A/C have eight edge-triggered D-type flip-flops

with individual D inputs and O outputs. The common buffered

Clock (CP) and Master Reset ( ) inputs load and reset

(clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D

input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding flip-flop’s O

output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the input. The

device is useful for applications where the true output only is

required and the Clock and Master Reset are common to all

storage elements.

FUNCTIONAL BLOCK DIAGRAM

2558 drw 01

PIN CONFIGURATIONS

Vcc

GND

P20-1

D20-1

SO20-2

E20-1

2558 drw 02

INDEX

L20-2

Vcc

GND

10 11 12 13

20 19

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST is a registered trademark of National Semiconductor Co.

DIP/SOIC/CERPACK

TOP VIEW

LCC

TOP VIEW

7.10 2

IDT54/74FCT273/A/C FAST CMOS

OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE

Inputs Outputs

Operating Mode CP D

N ON

Reset (Clear) L X X L

Load “1” H ↑ hH

Load “0” H ↑ lL

NOTES: 2558 tbl 06

H = HIGH voltage level steady-state

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock

transition

L = LOW voltage level steady state

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock

transition

X = Don’t care

↑ = LOW-to-HIGH clock transition

PIN DESCRIPTION

Pin Names Description

N Data Input

Master Reset (Active LOW)

CP Clock Pulse Input (Active Rising Edge)

N Data Outputs

2558 tbl 05

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

TERM

(2)

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect

to GND

TERM

(3)

Terminal Voltage –0.5 to VCC –0.5 to VCC V

with Respect

to GND

A Operating 0 to +70 –55 to +125 °C

Temperature

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

Temperature

T Power Dissipation 0.5 0.5 W

OUT DC Output Current 120 120 mA

NOTES: 2558 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability. No terminal voltage

may exceed V

CC by +0.5V unless otherwise noted.

2. Input and V

CC terminals only.

3. Outputs and I/O terminals only.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(1)

Conditions Typ. Max. Unit

IN Input Capacitance VIN = 0V 6 10 pF

OUT Output Capacitance VOUT = 0V 8 12 pF

NOTE: 2558 tbl 02

1. This parameter is guaranteed by characterization data and not tested.

7.10 3

IDT54/74FCT273/A/C FAST CMOS

OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

IH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V

IL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

IH Input HIGH Current VCC = Max. VI = VCC ——5µA

I = 2.7V — — 5

(4)

IIL Input LOW Current VI = 0.5V — — –5

(4)

VI = GND — — –5

IK Clamp Diode Voltage Vcc = Min., IN = –18mA — –0.7 –1.2 V

OS Short Circuit Current Vcc = Max.

(3)

, VO = GND –60 –120 — mA

OH Output HIGH Voltage Vcc = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

Vcc = Min. I

OH = –300µAVHC VCC —

IN = VIH or VIL IOH = –12mA MIL. 2.4 4.3 —

OH = –15mA COM’L. 2.4 4.3 —

OL Output LOW Voltage Vcc = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

Vcc = Min. I

OL = 300µA — GND VLC

(4)

VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5

OL = 48mA COM’L. — 0.3 0.5

NOTES: 2558 tbl 03

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

CC = 5.0V, +25°C ambient and maximum loading.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

Part #	54FCT273ADB
Description
Category	IC
Availability	Out of Stock
Qty	0

54FCT273ADB

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