Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

IH

/I

IL

HIGH/LOW Output I

OH

/I

OL

A

0

–A

3

A Operand Inputs 1.0/2.0 20 mA/

b

1.2 mA

B

0

–B

3

B Operand Inputs 1.0/2.0 20 mA/

b

1.2 mA

C

0

Carry Input 1.0/1.0 20 mA/

b

0.6 mA

S

0

–S

3

Sum Outputs 50/33.3

b

1 mA/20 mA

C

4

Carry Output 50/33.3

b

1 mA/20 mA

Functional Description

The ’F283 adds two 4-bit binary words (A plus B) plus the

incoming Carry (C

0

). The binary sum appears on the Sum

(S

0

–S

3

) and outgoing carry (C

4

) outputs. The binary weight

of the various inputs and outputs is indicated by the sub-

script numbers, representing powers of two.

2

0

(A

0

a

B

0

a

C

0

)

a

2

1

(A

1

a

B

1

)

a

2

2

(A

2

a

B

2

)

a

2

3

(A

3

a

B

3

)

e

S

0

a

2S

1

a

4S

2

a

8S

3

a

16C

4

Where (

a

)

e

plus

Interchanging inputs of equal weight does not affect the op-

eration. Thus C

0

,A

0

,B

0

can be arbitrarily assigned to pins

5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages.

Due to the symmetry of the binary add function, the ’F283

can be used either with all inputs and outputs active HIGH

(positive logic) or with all inputs and outputs active LOW

(negative logic). See

Figure 1

. Note that if C

0

is not used it

must be tied LOW for active HIGH logic or tied HIGH for

active LOW logic.

Due to pin limitations, the intermediate carries of the ’F283

are not brought out for use as inputs or outputs. However,

other means can be used to effectively insert a carry into, or

bring a carry out from, an intermediate stage.

Figure 2

shows how to make a 3-bit adder. Tying the operand inputs

of the fourth adder (A

3

,B

3

) LOW makes S

3

dependent only

on, and equal to, the carry from the third adder. Using some-

what the same principle,

Figure 3

shows a way of dividing

the ’F283 into a 2-bit and a 1-bit adder. The third stage

adder (A

2

,B

2

,S

2

) is used merely as a means of getting a

carry (C

10

) signal into the fourth stage (via A

2

and B

2

) and

bringing out the carry from the second stage on S

2

. Note

that as long as A

2

and B

2

are the same, whether HIGH or

LOW, they do not influence S

2

. Similarly, when A

2

and B

2

are the same the carry into the third stage does not influ-

ence the carry out of the third stage.

Figure 4

shows a meth-

od of implementing a 5-input encoder, where the inputs are

equally weighted. The outputs S

0

,S

1

and S

2

present a bina-

ry number equal to the number of inputs I

1

–I

5

that are true.

Figure 5

shows one method of implementing a 5-input ma-

jority gate. When three or more of the inputs I

1

–I

5

are true,

the output M

5

is true.

C

0

A

0

A

1

A

2

A

3

B

0

B

1

B

2

B

3

S

0

S

1

S

2

S

3

C

4

Logic Levels L LHLHHLLHHHLLH

Active HIGH 0 0101100111001

Active LOW 1 1010011000110

Active HIGH: 0

a

10

a

9

e

3

a

16 Active LOW: 1

a

5

a

6

e

12

a

0

FIGURE 1. Active HIGH versus Active LOW Interpretation

2