National Semiconductor Corp 54F153DM

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TL/F/9482
54F/74F153 Dual 4-Input Multiplexer
December 1994
54F/74F153
Dual 4-Input Multiplexer
General Description
The ’F153 is a high-speed dual 4-input multiplexer with com-
mon select inputs and individual enable inputs for each sec-
tion. It can select two lines of data from four sources. The
two buffered outputs present data in the true (non-inverted)
form. In addition to multiplexer operation, the ’F153 can
generate any two functions of three variables.
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F153PC N16E 16-Lead (0.300
×
Wide) Molded Dual-In-Line
54F153DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F153SC (Note 1) M16A 16-Lead (0.150
×
Wide) Molded Small Outline, JEDEC
74F153SJ (Note 1) M16D 16-Lead (0.300
×
Wide) Molded Small Outline, EIAJ
54F153FM (Note 2) W16A 16-Lead Cerpack
54F153LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13
×
reel. Use suffix
e
SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols Connection Diagrams
TL/F/94823
IEEE/IEC
TL/F/94825
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/94821
Pin Assignment
for LCC
TL/F/94822
TRI-STATE
É
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
I
0a
–I
3a
Side A Data Inputs 1.0/1.0 20 mA/
b
0.6 mA
I
0b
–I
3b
Side B Data Inputs 1.0/1.0 20 mA/
b
0.6 mA
S
0
,S
1
Common Select Inputs 1.0/1.0 20 mA/
b
0.6 mA
E
a
Side A Enable Input (Active LOW) 1.0/1.0 20 mA/
b
0.6 mA
E
b
Side B Enable Input (Active LOW) 1.0/1.0 20 mA/
b
0.6 mA
Z
a
Side A Output 50/33.3
b
1 mA/20 mA
Z
b
Side B Output 50/33.3
b
1 mA/20 mA
Functional Description
The ’F153 is a dual 4-input multiplexer. It can select two bits
of data from up to four sources under the control of the
common Select inputs (S
0
,S
1
). The two 4-input multiplexer
circuits have individual active LOW Enables (E
a
,E
b
) which
can be used to strobe the outputs independently. When the
Enables (E
a
,E
b
) are HIGH, the corresponding outputs (Z
a
,
Z
b
) are forced LOW. The ’F153 is the logic implementation
of a 2-pole, 4-position switch, where the position of the
switch is determined by the logic levels supplied to the two
Select inputs. The logic equations for the outputs are as
follows:
Z
a
e
E
a
#
(I
0a
#
S
1
#
S
0
a
I
1a
#
S
1
#
S
0
a
I
2a
#
S
1
#
S
0
a
I
3a
#
S
1
#
S
0
)
Z
b
e
E
b
#
(I
0b
#
S
1
#
S
0
a
I
1b
#
S
1
#
S
0
a
I
2b
#
S
1
#
S
0
a
I
3b
#
S
1
#
S
0
)
The ’F153 can be used to move data from a group of regis-
ters to a common output bus. The particular register from
which the data came would be determined by the state of
the Select inputs. A less obvious application is as a function
generator. The ’F153 can generate two functions of three
variables. This is useful for implementing highly irregular
random logic.
Truth Table
Select
Inputs (a or b) Output
Inputs
S
0
S
1
E I
0
I
1
I
2
I
3
Z
XXHXXXX L
LLLLXXX L
LLLHXXX H
HLLXLXX L
HLLXHXX H
LHLXXLX L
LHLXXHX H
HHLXXXL L
HHLXXXH H
H
e
HIGH Voltage Level
L
e
LOW
X
e
Immaterial
2
Logic Diagram
TL/F/94824
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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