XC9572XL High Performance CPLD

4 www.xilinx.com DS057 (v2.0) April 3, 2007

Product Specification

R

AC Characteristics

Symbol Parameter

XC9572XL-5 XC9572XL-7 XC9572XL-10

UnitsMin Max Min Max Min Max

T

PD

I/O to output valid - 5.0 - 7.5 - 10.0 ns

T

SU

I/O setup time before GCK 3.7 - 4.8 - 6.5 - ns

T

H

I/O hold time after GCK 0 - 0 - 0 - ns

T

CO

GCK to output valid - 3.5 - 4.5 - 5.8 ns

f

SYSTEM

Multiple FB internal operating frequency - 178.6 - 125.0 - 100.0 MHz

T

PSU

I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns

T

PH

I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns

T

PCO

P-term clock output valid - 5.5 - 7.7 - 10.2 ns

T

OE

GTS to output valid - 4.0 - 5.0 - 7.0 ns

T

OD

GTS to output disable - 4.0 - 5.0 - 7.0 ns

T

POE

Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns

T

POD

Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns

T

AO

GSR to output valid - 10.0 - 12.0 - 14.5 ns

T

PAO

P-term S/R to output valid - 10.5 - 12.6 - 15.3 ns

T

WLH

GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns

T

APRPW

Asynchronous preset/reset pulse width

(High or Low)

5.0 - 6.5 - 7.0 - ns

T

PLH

P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns

Figure 3: AC Load Circuit

Device Output

Output Type V

TEST

3.3V

2.5V

V

TEST

R

1

320 Ω

250 Ω

R

1

R

2

C

L

R

2

360 Ω

660 Ω

C

L

35 pF

DS058_03_081500

V

CCIO

3.3V

2.5V

XC9572XL High Performance CPLD

DS057 (v2.0) April 3, 2007 www.xilinx.com 5

Product Specification

R

Internal Timing Parameters

Symbol Parameter

XC9572XL-5 XC9572XL-7 XC9572XL-10

UnitsMin Max Min Max Min Max

Buffer Delays

T

IN

Input buffer delay - 1.5 - 2.3 - 3.5 ns

T

GCK

GCK buffer delay - 1.1 - 1.5 - 1.8 ns

T

GSR

GSR buffer delay - 2.0 - 3.1 - 4.5 ns

T

GTS

GTS buffer delay - 4.0 - 5.0 - 7.0 ns

T

OUT

Output buffer delay - 2.0 - 2.5 - 3.0 ns

T

EN

Output buffer enable/disable delay - 0 - 0 - 0 ns

Product Term Control Delays

T

PTCK

Product term clock delay - 1.6 - 2.4 - 2.7 ns

T

PTSR

Product term set/reset delay - 1.0 - 1.4 - 1.8 ns

T

PTTS

Product term 3-state delay - 5.5 - 7.2 - 7.5 ns

Internal Register and Combinatorial Delays

T

PDI

Combinatorial logic propagation delay - 0.5 - 1.3 - 1.7 ns

T

SUI

Register setup time 2.3 - 2.6 - 3.0 - ns

T

HI

Register hold time 1.4 - 2.2 - 3.5 - ns

T

ECSU

Register clock enable setup time 2.4 - 2.6 - 3.0 - ns

T

ECHO

Register clock enable hold time 1.4 - 2.2 - 3.5 - ns

T

COI

Register clock to output valid time - 0.4 - 0.5 - 1.0 ns

T

AOI

Register async. S/R to output delay - 6.0 - 6.4 - 7.0 ns

T

RAI

Register async. S/R recover before clock 5.0 7.5 10.0 ns

T

LOGI

Internal logic delay - 1.0 - 1.4 - 1.8 ns

T

LOGILP

Internal low power logic delay - 5.0 - 6.4 - 7.3 ns

Feedback Delays

T

F

Fast CONNECT II feedback delay - 1.9 - 3.5 - 4.2 ns

Time Adders

T

PTA

Incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns

T

SLEW

Slew-rate limited delay - 3.0 - 4.0 - 4.5 ns

XC9572XL High Performance CPLD

6 www.xilinx.com DS057 (v2.0) April 3, 2007

Product Specification

R

XC9572XL I/O Pins

(4)

Func-

tion

Block

Macro-

cell PC44 VQ44 CS48 VQ64 TQ100

BScan

Order

Func

-tion

Block

Macro-

cell PC44VQ44CS48VQ64TQ100

BScan

Order

1 1 ----16213 3 1 ----41105

1 2 1 39 D7 8 13 210 3 2 11 5 B5 22 32 102

1 3 - - D4 12 18 207 3 3 - - C4 31 49 99

1 4 ---1320204 3 4 ---325096

1 5 2 40 D6 9 14 201 3 5 12 6 A4 24 35 93

16341C7101519836---345390

1 7 ----25195 3 7 ----5487

18442C6111719238137B4253784

195

(1)

43

(1)

B7

(1)

15

(1)

22

(1)

18939148A3274281

1 10 - - - 18 28 186 3 10 - - D3 39 60 78

1116

(1)

44

(1)

B6

(1)

16

(1)

23

(1)

183 3 11 18 12 B2 33 52 75

1 12 ---2333180 3 12 ---406172

1 13 ----36177 3 13 ----6369

1147

(1)

1

(1)

A7

(1)

17

(1)

27

(1)

174 3 14 19 13 B1 35 55 66

11582A61929171 3152014C2365663

1 16 ----39168 3 162418D2426460

11793C52030165 3172216C3385857

1 18 ----40162 3 18 ----5954

2 1 ----87159 4 1 ----6551

2 2 35 29 F4 60 94 156 4 2 25 19 E1 43 67 48

2 3 ---5891153 4 3 ---467145

2 4 ---5993150 4 4 ---477242

2 5 36 30 G5 61 95 147 4 5 26 20 E2 44 68 39

2 6 37 31 F5 62 96 144 4 6 - - E4 49 76 36

2 7 ----3

(2)

141 4 7 ----7733

2 8 38 32 G6 63 97 138 4 8 27 21 F1 45 70 30

2939

(1)

33

(1)

G7

(1)

64

(1)

99

(1)

135 4 9 ----6627

2 10 ---11132 4 10 ---518124

21140

(1)

34

(1)

F6

(1)

2

(1)

4

(1)

129 4 11 28 22 G1 48 74 21

2 12 ---46126 4 12 ---528218

2 13 ----8123 4 13 ----8515

21442

(3)

36

(3)

E6

(3)

5

(3)

9

(3)

120 4 14 29 23 F2 50 78 12

2 15 43 37 E7 6 11 117 4 15 33 27 E3 56 89 9

2 16 ----10114 4 16 ----866

2174438E5712111 4173428G457903

2 18 ----92108 4 18 ----790

Notes:

1. Global control pin.

2. GTS1 for TQ100.

3. GTS1 for PC44, VQ44, CS48, and VQ64.

4. The pin-outs are the same for Pb-free versions of packages.

Part #	XC9572XL-10VQG64C
Description	CPLD XC9500XL Family 1.6K Gates 72 Macro Cells 100MHz 0.35
Category	IC
Availability	Out of Stock
Qty	0

XC9572XL-10VQG64C

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