W25Q128FV
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6.1.3 Quad SPI Instructions
The W25Q128FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O
(E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of
ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus
(XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the
/WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile
Quad Enable bit (QE) in Status Register-2 to be set.
6.1.4 QPI Instructions
The W25Q128FV supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI
protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial
clocks are required. This can significantly reduce the SPI instruction overhead and improve system
performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only
one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to
switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction,
the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile
Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and
DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. See Figure 3 for the device operation modes.
6.1.5 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q128FV operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register-2 is used to
determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD,
when QE=1, the pin will become an I/O pin, /HOLD function is no longer available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
