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W25Q128FVFIG

Part # W25Q128FVFIG
Description NOR Flash Serial-SPI 3.3V 128Mbit 16M x 8bit 7ns 16-Pin SO
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

W25Q128FV
Publication Release Date: October 01, 2012
- 6 - Revision D
3. PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pin Configuration SOIC / VSOP 208-mil
Figure 1a. W25Q128FV Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code S, T)
3.2 Pad Configuration WSON 6x5-mm / 8x6-mm
Figure 1b. W25Q128FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code P, E)
3.3 Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm
PIN NO. PIN NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)
(1)
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)
(2)
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)
(1)
6 CLK I Serial Clock Input
7
/HOLD or /RESET
(IO3)
I/O Hold or Reset Input (Data Input Output 3)
(2)
8 VCC Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
W25Q128FV
- 7 -
3.4 Pin Configuration SOIC 300-mil
Figure 1c. W25Q128FV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.5 Pin Description SOIC 300-mil
PIN NO. PIN NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)
(2)
2 VCC Power Supply
3 /RESET I Reset Input
(3)
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1)
(1)
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)
(2)
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0)
(1)
16 CLK I Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register.
W25Q128FV
Publication Release Date: October 01, 2012
- 8 - Revision D
3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Figure 1d. W25Q128FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C)
3.7 Ball Description TFBGA 8x6-mm
BALL NO. PIN NAME I/O FUNCTION
B2 CLK I Serial Clock Input
B3 GND Ground
B4 VCC Power Supply
C2 /CS I Chip Select Input
C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)
(2)
D2 DO (IO1) I/O Data Output (Data Input Output 1)
(1)
D3 DI (IO0) I/O Data Input (Data Input Output 0)
(1)
D4
/HOLD or /RESET
(IO3)
I/O Hold or Reset Input (Data Input Output 3)
(2)
Multiple NC No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
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