Thermal Shutdown
Small Signal Model for Loop Response
VSENSE
COMP
VOUT
R1
R3
C1
C2
R2
Coea
Roea
gm
1300 mA/V
0.8 V
PowerStage
PH
R
ESR
C
O
R
L
b
a
c
16 A/V
Simple Small Signal Model for Peak Current Mode Control
TPS54620
SLVS949 – MAY 2009 ........................................................................................................................................................................................................
www.ti.com
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175 ° C typically. The device reinitiates the power up sequence when the junction temperature drops below 165 ° C
typically.
Figure 30 shows an equivalent model for the device control loop which can be modeled in a circuit simulation
program to check frequency response and transient responses. The error amplifier is a transconductance
amplifier with a gm of 1300 µ A/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Roea (2.38 M Ω ) and capacitor Coea (20.7 pF) model the open loop gain and frequency
response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of
the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the
overall loop. The dynamic loop response can be checked by replacing the R
L
with a current source with the
appropriate load step amplitude and step rate in a time domain analysis.
Figure 30. Small Signal Model for Loop Response
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 30 ) is the power stage
transconductance (gm
ps
) which is 16 A/V for the device. The DC gain of the power stage is the product of gm
ps
and the load resistance (R
L
) as shown in Equation 11 with resistive loads. As the load current increases, the DC
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with load current (see Equation 12 ). The combined effect is highlighted by the dashed line in Figure 32 .
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
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