Adjustable Switching Frequency (RT Mode)

( )

0.997

W × -Rrt(k ) = 48000 Fsw kHz

(4)

Fsw − Oscillator Frequency − kHz

100

150

200

250

200 400 600 800 1000 1200 1400 1600

RT − Resistance − kΩ

Synchronization (CLK mode)

RT/CLK

TPS54620

Rrt

RT/CLK

modeselect

TPS54620

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........................................................................................................................................................................................................ SLVS949 – MAY 2009

In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of

the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kOhm and minimum of 29 k Ω

respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized

to the external clock frequency with PLL.

The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch

from the RT mode to CLK mode.

To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 20 . To

reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply

efficiency and minimum controllable on time should be considered.

Figure 20. RT Set Resistor vs Switching Frequency

An internal Phase Locked Loop (PLL) has been implemented to allow synchronization between 200kHz and

1600kHz, and to easily switch from RT mode to CLK mode.

To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty

cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8V and higher than 2.0V.

The start of the switching cycle is synchronized to the falling edge of RT/CLK pin.

In applications where both RT mode and CLK mode are needed, the device can be configured as shown in

Figure 21 . Before the external clock is present, the device works in RT mode and the switching frequency is set

by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the

SYNC pin is pulled above the RT/CLK high threshold (2.0V), the device switches from the RT mode to the CLK

mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external

clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching

frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.

Figure 21. Works with Both RT mode and CLK mode

Product Folder Link(s) :TPS54620

Slow Start (SS/TR)

Css(nF) Vref(V)

Tss(ms) =

Iss( A)

(5)

Power Good (PWRGD)

Bootstrap Voltage (BOOT) and Low Dropout Operation

Sequencing (SS/TR)

TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

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The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference

voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start

time. The device has an internal pull-up current source of 2.3 µ A that charges the external slow start capacitor.

The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in

Equation 5 . The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3 µ A.

When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the

device stops switching and enters low current operation. At the subsequent power up, when the shutdown

condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring

propper soft start behavior.

The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal

voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a

pull-up resistor between the values of 10k Ω and 100k Ω to a voltage source that is 5.5V or less. The PWRGD is

in a defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The

PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V.

The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal

reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN

pin is pulled low or the SS/TR pin is below 1.4V.

The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH

pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT

pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor

should be 0.1 µ F. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher

is recommended because of the stable characteristics over temperature and voltage.

To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin

voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1V. When the voltage between BOOT

and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side

MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails

100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4V.

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD

pins.

The sequential method is illustrated in Figure 22 using two TPS54620 devices. The power good of the first

device is coupled to the EN pin of the second device which enables the second power supply once the primary

supply reaches regulation. Figure 23 shows the results of Figure 22 .

Product Folder Link(s) :TPS54620

SS/TR

PWRGD

SS/TR

PWRGD

TPS54620

PWRGD=2V/div

EN=2V/div

Vout1=1V/div

Vout2=1v/div

Time=20msec/div

EN=2V/div

Vout1=1V/div

Vout2=1v/div

Time=20msec/div

SS/TR

TPS54620

PWRGD

SS/TR

PWRGD

TPS54620

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Figure 22. Sequencial Start Up Sequence Figure 23. Sequential Start Up using EN and PWRGD

Figure 24 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices

together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start

time the pull up current source must be doubled in Equation 5 . Figure 25 shows the results of Figure 24 .

Figure 24. Ratiometric Start Up Sequence Figure 25. Ratio-metric Startup using Coupled SS/TR

Pins

Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network

of R1 and R2 shown in Figure 26 to the output of the power supply that needs to be tracked or another voltage

reference source. Using Equation 6 and Equation 7 , the tracking resistors can be calculated to initiate the Vout2

slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and

Vout2.

To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2

reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 8 results in a

positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.

Figure 27 and Figure 28 show the results for positive deltaV and negtive deltaV respectively.

The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to

VSENSE offset (Vssoffset, 29mV) in the slow start circuit and the offset created by the pullup current source (Iss,

2.3 µ A) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. Figure 29 shows

the result when deltaV = 0V.

Product Folder Link(s) :TPS54620

Part #	TPS54620RGYR
Description	Conv DC-DC Single Step Down 1.6V to 17V 14-Pin VQFN EP T/R
Category	IC
Availability	Out of Stock
Qty	0

TPS54620RGYR

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