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SN74VMEH22501A-EP

SCES625A –FEBRUARY 2005–REVISED NOVEMBER 2015

SN74VMEH22501A-EP 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers

With Split LVTTL Port, Feedback Path, and 3-State Outputs

1 Features 2 Applications

• Controlled Baseline

• Industrial Controls

• Telecommunications

– One Assembly/Test Site, One Fabrication Site

• Instrumentation Systems

• Enhanced Diminishing Manufacturing Sources

(DMS) Support

3 Description

• Enhanced Product-Change Notification

The SN74VMEH22501A-EP 8-bit universal bus

• Qualification Pedigree

(1)

transceiver has two integral 1-bit three-wire bus

• Member of the Texas Instruments Widebus™

transceivers and is designed for 3.3-V V

operation

Family

with 5-V tolerant inputs. The UBT transceiver allows

• UBT™ Transceiver Combines D-Type Latches

transparent, latched, and flip-flop modes of data

transfer, and the separate LVTTL input and outputs

and D-Type Flip-Flops for Operation in

on the bus transceivers provide a feedback path for

Transparent, Latched, or Clocked Modes

control and diagnostics monitoring. This device

• OEC™ Circuitry Improves Signal Integrity and

provides a high-speed interface between cards

Reduces Electromagnetic Interference (EMI)

operating at LVTTL logic levels and VME64, VME64x,

• Compliant With VME64, 2eVME, and 2eSST

or VME320

(2)

backplane topologies.

Protocols Validated at T

= –40°C to 85°C

Device Information

(3)

• Bus Transceiver Split LVTTL Port Provides a

PART NUMBER PACKAGE BODY SIZE (NOM)

Feedback Path for Control and Diagnostics

TSSOP (48) 4.40 mm × 9.70 mm

Monitoring

SN74VMEH22501A-EP

TVSOP (48) 6.10 mm × 12.50 mm

• I/O Interfaces are 5-V Tolerant

(1) Component qualification in accordance with JEDEC and

• B-Port Outputs (–48 mA/64 mA)

industry standards to ensure reliable operation over an

• Y and A-Port Outputs (–12 mA/12 mA)

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

• I

off

, Power-Up 3-State, and BIAS V

Support Live

temperature cycle, autoclave or unbiased HAST,

Insertion

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

• Bus Hold on 3A-Port Data Inputs

justifying use of this component beyond specified

• 26-Ω Equivalent Series Resistor on 3A Ports and

performance and environmental limits.

Y Outputs

(2) VME320 is a patented backplane construction by Arizona

Digital, Inc.

• Flow-Through Architecture Facilitates Printed

(3) For all available packages, see the orderable addendum at

Circuit Board Layout

the end of the data sheet.

• Distributed V

and GND Pins Minimize High-

Speed Switching Noise Logic Diagram (Positive Logic)

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Pin numbers shown for DGG and DGV

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74VMEH22501A-EP

SCES625A –FEBRUARY 2005–REVISED NOVEMBER 2015

www.ti.com

Table of Contents

7.19 Skew Characteristics for UBT (M Version) ........... 15

1 Features.................................................................. 1

7.20 Skew Characteristics for Bus Transceiver (I

2 Applications ........................................................... 1

Version).................................................................... 17

3 Description ............................................................. 1

7.21 Skew Characteristics for UBT (I Version) ............. 17

4 Revision History..................................................... 2

7.22 Skew Characteristics for Bus Transceiver (I

5 Description (continued)......................................... 3

Version).................................................................... 17

6 Pin Configuration and Functions......................... 4

7.23 Skew Characteristics for UBT (I Version) ............. 18

7.24 Maximum Data Transfer Rates............................. 18

7 Specifications......................................................... 6

7.25 Typical Characteristics.......................................... 19

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

8 Parameter Measurement Information ................ 20

7.3 Recommended Operating Conditions....................... 7

8.1 Distributed-Load Backplane Switching

Characteristics ......................................................... 20

7.4 Thermal Information.................................................. 7

9 Detailed Description............................................ 23

7.5 Electrical Characteristics........................................... 8

9.1 Overview ................................................................. 23

7.6 Live-Insertion Specifications ..................................... 9

9.2 Functional Block Diagram ....................................... 24

7.7 Timing Requirements for UBT Transceiver (I

Version)...................................................................... 9

9.3 Feature Description................................................. 25

7.8 Switching Characteristics for Bus Transceiver

9.4 Device Functional Modes........................................ 27

Function (I Version).................................................. 10

10 Application and Implementation........................ 28

7.9 Switching Characteristics for Bus Transceiver

10.1 Application Information.......................................... 28

Function (M Version)................................................ 10

10.2 Typical Application ............................................... 28

7.10 Switching Characteristics for UBT Transceiver (I

11 Power Supply Recommendations ..................... 30

Version).................................................................... 11

7.11 Switching Characteristics for UBT Transceiver (M

12 Layout................................................................... 30

Version).................................................................... 12

12.1 Layout Guidelines ................................................. 30

7.12 Switching Characteristics for Bus Transceiver

12.2 Layout Example .................................................... 31

Function (I Version).................................................. 12

13 Device and Documentation Support ................. 32

7.13 Switching Characteristics for UBT (I Version)....... 13

13.1 Device Support...................................................... 32

7.14 Switching Characteristics for Bus Transceiver

13.2 Related Links ........................................................ 32

Function (I Version).................................................. 13

13.3 Community Resources.......................................... 32

7.15 Switching Characteristics for UBT (I Version)....... 13

13.4 Trademarks........................................................... 32

7.16 Skew Characteristics for Bus Transceiver (I

13.5 Electrostatic Discharge Caution............................ 32

Version).................................................................... 14

13.6 Glossary................................................................ 32

7.17 Skew Characteristics for Bus Transceiver (M

Version).................................................................... 15

14 Mechanical, Packaging, and Orderable

7.18 Skew Characteristics for UBT (I Version) ............. 15

Information ........................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (February 2005) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Removed Ordering Information table. ................................................................................................................................... 1

• Added junction temperature and removed package thermal impedance from Absolute Maximum Ratings ......................... 6

• Added different conditions and results for I and M versions to the Specifications ................................................................ 7

• Updated the V

test condition for I

OZ(PU/PD)

.......................................................................................................................... 8

• Added Community Resources ............................................................................................................................................. 32

Product Folder Links: SN74VMEH22501A-EP

SN74VMEH22501A-EP

www.ti.com

SCES625A –FEBRUARY 2005–REVISED NOVEMBER 2015

5 Description (continued)

The SN74VMEH22501A-EP device is pin-for-pin compatible to the SN74VMEH22501 device (SCES357), but

operates at a wider operating temperature range.

High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been

designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive

loads and include pseudo-ETL input thresholds (½ V

±50 mV) for increased noise immunity. These

specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5.

With proper design of a 21-slot VME system, a designer can achieve 320-MB transfer rates on linear backplanes

and, possibly, 1-GB transfer rates on the VME320 backplane.

All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.

Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not

provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the

bus-hold circuitry is not recommended.

This device is fully specified for live-insertion applications using I

off

, power-up 3-state, and BIAS V

. The I

off

circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-

state circuitry places the outputs in the high-impedance state during power up and power down, which prevents

driver conflict. The BIAS V

circuitry precharges and preconditions the B-port input/output connections,

preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-

insertion capability.

When V

is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, output-enable ( OE and OEBY) inputs should be tied

to V

through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown

resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this

input.

Product Folder Links: SN74VMEH22501A-EP

Part #	501AMD
Description
Category	IC
Availability	Out of Stock
Qty	0

501AMD

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