Name: SN74AUC1G04DCKR
SKU: SN74AUC1G04DCKR
Price: 0.07853 USD
Availability: InStock



  

SCES370L − SEPTEMBER 2001 − REVISED NOVEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Available in the Texas Instruments

NanoStar and NanoFree Packages

D Optimized for 1.8-V Operation and Is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

D I

off

Supports Partial-Power-Down Mode

Operation

D Sub 1-V Operable

D Max t

of 2.2 ns at 1.8 V

D Low Power Consumption, 10-µA Max I

D ±8-mA Output Drive at 1.8 V

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This single inverter gate is operational at 0.8-V to 2.7-V V

, but is designed specifically for 1.65-V to 1.95-V

operation.

The SN74AUC1G04 performs the Boolean function Y = A

NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

NanoStar − WCSP (DSBGA)

0.17-mm Small Bump − YEA

SN74AUC1G04YEAR

NanoFree − WCSP (DSBGA)

0.17-mm Small Bump − YZA (Pb-free)

Tape and reel

SN74AUC1G04YZAR

_ _ _UC_

−40°C to 85°C

NanoStar − WCSP (DSBGA)

0.23-mm Large Bump − YEP

Tape and reel

SN74AUC1G04YEPR

_ _ _UC_

NanoFree − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

SN74AUC1G04YZPR

SOT (SOT-23) − DBV Tape and reel SN74AUC1G04DBVR U04_

SOT (SC-70) − DCK Tape and reel SN74AUC1G04DCKR UC_

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

‡

DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,

and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition

(1 = SnPb,

• = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

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DBV OR DCK PACKAGE

(TOP VIEW)

GND

NC − No internal connection

DNU − Do not use

GND

DNU

YEA, YEP, YZA, OR YZP PACKAGE

(BOTTOM VIEW)



  

SCES370L − SEPTEMBER 2001 − REVISED NOVEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

For more information about AUC Little Logic devices, please refer to the TI application report, Applications of

Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

FUNCTION TABLE

INPUT

OUTPUT

H L

L H

logic diagram (positive logic)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

−0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) −0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, V

(see Note 1) −0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Note 1) −0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

YEA/YZA package 154°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .

YEP/YZP package 132°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.



  

SCES370L − SEPTEMBER 2001 − REVISED NOVEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

MIN MAX UNIT

Supply voltage 0.8 2.7 V

= 0.8 V V

High-level input voltage

= 1.1 V to 1.95 V

0.65 × V

High-level input voltage

= 2.3 V to 2.7 V 1.7

= 0.8 V 0

Low-level input voltage

= 1.1 V to 1.95 V

0.35 × V

Low-level input voltage

= 2.3 V to 2.7 V 0.7

Input voltage 0 3.6 V

Output voltage 0 V

= 0.8 V −0.7

= 1.1 V −3

High-level output current

= 1.4 V

−5

High-level output current

= 1.65 V −8

= 2.3 V −9

= 0.8 V 0.7

= 1.1 V 3

Low-level output current

= 1.4 V

Low-level output current

= 1.65 V 8

= 2.3 V 9

∆t/∆v Input transition rise or fall rate 20 ns/V

Operating free-air temperature −40 85 °C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER TEST CONDITIONS

MIN TYP

†

MAX UNIT

= −100 µA 0.8 V to 2.7 V V

−0.1

= −0.7 mA 0.8 V 0.55

= −3 mA 1.1 V 0.8

= −5 mA 1.4 V 1

= −8 mA 1.65 V 1.2

= −9 mA 2.3 V 1.8

= 100 µA 0.8 V to 2.7 V 0.2

= 0.7 mA 0.8 V 0.25

= 3 mA 1.1 V 0.3

= 5 mA 1.4 V 0.4

= 8 mA 1.65 V 0.45

= 9 mA 2.3 V 0.6

A input V

= V

or GND 0 to 2.7 V ±5 µA

off

or V

= 2.7 V 0 ±10 µA

= V

or GND, I

= 0 0.8 V to 2.7 V 10 µA

= V

or GND 2.5 V 3 pF

†

All typical values are at T

= 25°C.

Part #	SN74AUC1G04DCKR
Description	Inverter 1-Element CMOS 5-PinSC-70 T/R (Alt: SN74AUC1G04D
Category	IC
Availability	In Stock
Qty	1430

Qty	Price
1 - 300	$0.07853
301 - 600	$0.06246
601 - 900	$0.05890
901 - 1,201	$0.05473
1,202 +	$0.04878

SN74AUC1G04DCKR

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