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SY100E451JC

Part # SY100E451JC
Description IC D-TYPE POS TRG SNGL 28PLCC
Category IC
Availability In Stock
Qty 332
Qty Price
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94 - 141 $5.48071
142 + $4.88498
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SYNERGY
Date Code: 02
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SYNERGY
Date Code: 9132
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

6-BIT REGISTER
DIFFERENTIAL DATA CLOCK
DESCRIPTION
The SY10/100E451 offer six D-type flip-flops with single-
ended outputs and differential data and clock inputs,
designed for use in new, high-performance ECL systems.
The registers are triggered by the rising edge of the CLK
input.
A logic HIGH on the Master Reset (MR) input resets all
outputs to a logic LOW. The VBB output is provided for use
as a reference voltage for single-ended reception of ECL
signals to that device only. When used for this purpose, it
is recommended that VBB is decoupled to VCC via a 0.01µF
capacitor.
FEATURES
1100MHz min. toggle frequency
Extended 100E VEE range of –4.2V to –5.5V
Differential inputs: data and clock
VBB output for single-ended use
Asynchronous Master Reset
Fully compatible with industry standard 10KH,
100K ECL levels
Internal 75K input pulldown resistors
Fully compatible with Motorola MC10E/100E451
Available in 28-pin PLCC package
SY10E451
SY100E451
Rev.: C Amendment: /1
Issue Date: February, 1998
BLOCK DIAGRAM
D
R
D
R
D
R
D
R
D
R
D
R
Q
0
Q1
Q2
Q3
Q4
Q5
MR
D
0
D1
D2
D3
D4
D5
VBB
CLK
D
0
CLK
D1
D2
D3
D4
D5
Pin Function
D0–D5 + Data Input
D0–D5 – Data Input
CLK + Clock Input
CLK – Clock Input
MR Master Reset Input
VBB VBB Output
Q0–Q5 Data Outputs
V
CCO VCC to Output
PIN NAMES
PIN CONFIGURATION
TOP VIEW
PLCC
J28-1
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25
24 23 22 21 20 19
5 6 7 8 9 10 11
V
CC
Q
5
Q
4
Q
1
Q
3
Q
2
V
CCO
V
CCO
D
4
D
5
D
3
D
5
D
4
D
3
V
CCO
Q
0
D
1
D
2
D
0
D
1
D
2
V
EE
D
0
MR
NC
CLK
V
BB
CLK
1
2
SY10E451
SY100E451
Micrel
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = 25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
V
BB Output Reference Voltage V
10E 1.38 —–1.27 1.35 —–1.25 1.31 —–1.19
100E 1.38 —–1.26 1.38 —–1.26 1.38 —–1.26
IIH Input HIGH Current ——150 ——150 ——150 µA
I
EE Power Supply Current mA
10E 84 101 84 101 84 101
100E 84 101 84 101 97 116
V
CMR Common Mode Range 2.0 —–0.4 2.0 —–0.4 2.0 —–0.4 V 1
NOTE:
1. V
CMR is referenced to the most psitive side of the differential input signal. Normal operation is obtained when the "HIGH" input is within the VCMR
range and the input swing is greater than VPP(min) and < 1V.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
fMAX Max. Toggle Frequency 1100 1400 1100 1400 1100 1400 MHz
t
PLH Propagation Delay to Output ps
tPHL CLK (Diff) 475 650 800 475 650 800 475 650 800
CLK (SE) 425 650 850 425 650 850 425 650 850
MR 425 600 850 425 600 850 425 600 850
tS Set-up Time, D 150 100 150 100 150 100 ps
tH Hold Time, D 250 100 250 100 250 100 ps
VPP (AC) Minimum Input Swing 150 ——150 ——150 ——mV 1
tRR Reset Recovery Time 750 600 750 600 750 600 ps
t
PW Minimum Pulse Width 400 ——400 ——400 ——ps
CLK, MR
tskew Within-Device Skew 100 ——100 ——100 ps 2
t
r Rise/Fall Time 275 450 800 275 450 800 275 450 800 ps
tf 20% to 80%
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E451JC J28-1 Commercial
SY10E451JCTR J28-1 Commercial
SY100E451JC J28-1 Commercial
SY100E451JCTR J28-1 Commercial
NOTES:
1. Minimum input voltage for which AC parameters are guaranteed.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3
SY10E451
SY100E451
Micrel
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