Texas Instruments SN74LVC1G175DBVR

Cross Number:

Item Description: Flip Flop D-Type Pos-Edge 1-Element 6-Pin SOT-23 T/R (Alt:
Additional Information:

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.


  
  
SCES560AMARCH 2004 − REVISED AUGUST 2004
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Supports 5-V V
CC
Operation
D Inputs Accept Voltages to 5.5 V
D Max t
pd
of 4.3 ns at 3.3 V
D Low Power Consumption, 10-µA Max I
CC
D ±24-mA Output Drive at 3.3 V
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single D-type flip-flop is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D)
is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low
state, regardless of the clock edge or data on D.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000
SN74LVC1G175YEPR
_ _ _D6_
−40 C to 85 C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Reel of 3000
SN74LVC1G175YZPR
_ _ _D6_
−40°C to 85°C
SOT (SOT-23) − DBV
Reel of 3000 SN74LVC1G175DBVR
C75_
SOT (SOT-23) − DBV
Reel of 250 SN74LVC1G175DBVT
C75_
SOT (SC-70) − DCK
Reel of 3000 SN74LVC1G175DCKR
D6_
SOT (SC-70) − DCK
Reel of 250 SN74LVC1G175DCKT
D6_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, = Pb-free).
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
CLK
GND
D
CLR
V
CC
Q
3
2
1
4
5
6
D
GND
CLK
Q
V
CC
CLR
YEP OR YZP PACKAGE
(BOTTOM VIEW)
  ! " #$%! "  &$'(#! )!%*
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"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/  (( &%!%"*

  
  
SCES560AMARCH 2004 − REVISED AUGUST 2004
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
CLR CLK D Q
H L L
H HH
H H or L X Q
O
L X X L
logic diagram (positive logic)
Q
1
6
C1
D
CLR
CLK
D
R
3
4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) −0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DBV package 165°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 259°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 123°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V
CC
is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

  
  
SCES560AMARCH 2004 − REVISED AUGUST 2004
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage
Operating 1.65 5.5
V
CC
Supply voltage
Data retention only 1.5
V
CC
= 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
V
CC
= 2.3 V to 2.7 V 1.7
V
IH
High-level input voltage
V
CC
= 3 V to 3.6 V 2
V
CC
= 4.5 V to 5.5 V 0.7 × V
CC
V
CC
= 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
V
CC
= 2.3 V to 2.7 V 0.7
V
IL
Low-level input voltage
V
CC
= 3 V to 3.6 V 0.8
V
CC
= 4.5 V to 5.5 V 0.3 × V
CC
V
I
Input voltage 0 5.5 V
V
O
Output voltage 0 V
CC
V
V
CC
= 1.65 V −4
V
CC
= 2.3 V −8
I
OH
High-level output current
V
CC
= 3 V
−16
mA
I
OH
High-level output current
V
CC
= 3 V
−24
V
CC
= 4.5 V −32
V
CC
= 1.65 V 4
V
CC
= 2.3 V 8
I
OL
Low-level output current
V
CC
= 3 V
16
mA
I
OL
Low-level output current
V
CC
= 3 V
24
V
CC
= 4.5 V 32
V
CC
= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
t/v Input transition rise or fall rate
V
CC
= 3.3 V ± 0.3 V 10
ns/V
t/v
Input transition rise or fall rate
V
CC
= 5 V ± 0.5 V 10
T
A
Operating free-air temperature −40 85 °C
NOTE 4: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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