

Cirrus Logic, Inc. 1997

Cirrus Logic, Inc.

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

CS4330/31/33

8 Pin Stereo D/A Converter for Digital Audio

Features

Complete Stereo DAC System:

Interpolation, D/A, Output Analog Filtering

18-Bit Resolution

94 dB Dynamic Range

0.003% THD

Low Clock Jitter Sensitivity

Single +3 V or +5 V Power Supply

Filtered Line Level Outputs

Linear Phase Filtering

On-Chip Digital De-emphasis

Description

The CS4330, CS4331 and CS4333 are complete, stereo

digital-to-analog output systems including interpolation,

1-bit D/A conversion and output analog filtering in an 8-

pin package. These devices differ in the serial interface

format used to input audio data.

The CS4330, CS4331 and CS4333 are based on delta-

sigma modulation, where the modulator output controls

the reference voltage input to an ultra-linear analog low-

pass filter. This architecture allows for infinite adjustment

of sample rate between 2 kHz and 50 kHz while main-

taining linear phase response simply by changing the

master clock frequency.

The CS4330, CS4331 and CS4333 contain on-chip dig-

ital de-emphasis, operate from a single +3 V or +5 V

power supply, and consume only 60mW of power with a

3 V power supply. These features make them ideal for

portable CD players and other portable playback

systems.

ORDERING INFORMATION

See page 21.

LRCK

SDATA

DEM/SCLK

MCLK

VA+

AOUTL

AOUTR

Serial Input

Interface

Interpolator

De-emphasis

Delta-Sigma

Modulator

Delta-Sigma

Modulator

DAC

Voltage Reference

Analog

Low-Pass

Filter

Analog

Low-Pass

Filter

AGND

MAY ‘97

DS136F1

ANALOG CHARACTERISTICS

= 25°C; Logic "1" = VA+; Logic "0" = AGND; MCLK = 12.288 MHz;

Full-Scale Output Sine Wave, 991 Hz; Input Sample Rate = 48 kHz; Input Data = 18 Bits; SCLK = 3.072 MHz;

Measurement Bandwidth is 10 Hz to 20 kHz, unweighted; unless otherwise specified. Resistive load = 20 kΩ, capaci-

tive load = 100 pF)

CS4330/31/33-KS

VA +5V

CS4330/31/33-KS

VA +3V

CS4330/31/33-BS

VA +5V only

Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Units

Specified Temperature Range T

-10 to 70 -10 to 70 -40 to +85

°C

Resolution - - 18 - - 18 - - 18 Bits

Dynamic Performance

Dynamic Range (A-weighted) 90 94 - - 89 - 88 94 - dB

Total Harmonic Distortion - 0.003 0.007 - 0.003 - - .003 .008 %

Total Harmonic Distortion + Noise

0 dB Output,

-20 dB Output,

-60 dB Output

THD+N

-86

-72

-32

-81

-68

-28

-85

-67

-27

-80

-88

-86

-72

-32

-79

-66

-26

Deviation From Linear Phase (Note 1) -

± 0.5

-deg

Passband: to 0.05 dB corner (Note 2,3) 0 to 21.77 0 to 21.77 0 to 21.77 kHz

Frequency Response 10 Hz to 20 kHz(Note 1) -

± 0.1

-dB

Passband Ripple (Note 3) - -

±0.05

StopBand (Notes 2,3) 26.23 26.23 26.23 - - kHz

StopBand Attenuation (Note 4) 60 - - 60 - - 60 - - dB

Group Delay (Fs = Input Sample Rate) tgd - 16 / Fs - - 16 / Fs - - 16 / Fs - s

Interchannel Isolation (1 kHz) - 90 - - 90 - - 90 - dB

dc Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - - 0.1 - dB

Gain Error - -

± 10

Gain Drift - 250 - - 250 - - 250 -

ppm/°C

Analog Output

Full Scale Output Voltage 3.33 3.70 4.07 1.66 1.85 2.03 3.33 3.70 4.07 Vpp

Output Common Mode Voltage - 2.3 - - 1.3 - - 2.3 - VDC

Minimum Resistive Load - 10 - - 10 - - 20 -

kΩ

Maximum Capacitive Load - 100 - - 100 - - 100 - pF

Power Supplies

Power Supply Current: normal operation

power-down

IA+

µA

Power Dissipation normal operation

power-down

140

0.3

160

0.06

140

0.3

160

Power Supply Rejection Ratio (1 kHz) PSRR - 50 - - 50 - - 50 - dB

Notes: 1. Combined digital and analog filter characteristics.

2. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than

48 kHz, the 0.05 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

3. Digital filter characteristics.

4. Measurement Bandwidth is 10 Hz to Fs (kHz)

CS4330, CS4331, CS4333

2 DS136F1

SWITCHING CHARACTERISTICS

(TA = 25 °C; VA+ = 2.7V - 5.5V; Inputs: Logic 0 = 0V, Logic

1 = VA+, CL = 20 pF) Switching characteristics are guaranteed by characterization.

Parameter Symbol Min Typ Max Units

Input Sample Rate Fs 2 - 50 kHz

LRCK Duty Cycle (External SCLK only) (Note 5) 30 50 70 %

MCLK Pulse Width High MCLK / LRCK = 512 10 - 1000 ns

MCLK Pulse Width Low MCLK / LRCK = 512 15 - 1000 ns

MCLK Pulse Width High MCLK / LRCK = 384 21 - 1000 ns

MCLK Pulse Width Low MCLK / LRCK = 384 21 - 1000 ns

MCLK Pulse Width High MCLK / LRCK = 256 35 - 1000 ns

MCLK Pulse Width Low MCLK / LRCK = 256 39 - 1000 ns

External SCLK Mode

SCLK Pulse Width Low t

sclkl

20 - - ns

SCLK Pulse Width High t

sclkh

20 - - ns

SCLK Period t

sclkw

(

128

)

--ns

SCLK rising to LRCK edge delay t

slrd

20 - - ns

SCLK rising to LRCK edge setup time t

slrs

20 - - ns

SDATA valid to SCLK rising setup time t

sdlrs

20 - - ns

SCLK rising to SDATA hold time t

sdh

20 - - ns

Internal SCLK Mode

SCLK Period (Note 6) t

sclkw

SCLK

--ns

SCLK rising to LRCK edge t

sclkr -

sclkw

- µs

SDATA valid to SCLK rising setup time t

sdlrs

(

512

)

15 --ns

SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512 t

sdh

(

512

)

15 --ns

SCLK rising to SDATA hold time MCLK / LRCK = 384 t

sdh

(

384

)

15 --ns

Notes: 5. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period.

6. The SCLK / LRCK ratio may be either 32, 48, or 64.

CS4330, CS4331, CS4333

DS136F1 3

Part #	4333-KS
Description
Category	IC
Availability	Out of Stock
Qty	0

4333-KS

Related Items

Technical Document