7
FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE
AND FALL TIMES PER INVERTER FOR CD4050B
Typical Performance Curves (Continued)
10
6
10
4
10
3
10
2
1
10 10
2
10
3
10
4
10
5
T
A
= 25
o
C
POWER DISSIPATION PER INVERTER (µW)
t
r
, t
f
, INPUT RISE AND FALL TIME (ns)
SUPPLY VOLTAGE V
CC
= 5V FREQUENCY (f) = 10kHz
10
6
10
7
10
8
10
10
5
15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
15V; 1kHz
Test Circuits
FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT
NOTE: Test any one input with other inputs at V
CC
or V
SS
.
FIGURE 14. INPUT VOLTAGE TEST CIRCUIT
NOTE: Measure inputs sequentially, to both V
CC
and V
SS
connect
all unused inputs to either V
CC
or V
SS
.
FIGURE 15. INPUT CURRENT TEST CIRCUIT
In Terminal - 3, 5, 7, 9, 11, or 14
Out Terminal - 2, 4, 6, 10, 12 or 15
V
CC
Terminal - 1
V
SS
Terminal - 8
FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION
I
DD
V
CC
INPUTS
V
SS
V
CC
V
SS
V
CC
OUTPUTSINPUTS
V
IH
V
IL
V
SS
DVM
+
-
V
CC
OUTPUTSINPUTS
V
CC
V
SS
V
SS
I
V
CC
= 5V
OUTPUT
INPUTS
10V = V
IH
0 = V
IL
V
SS
TO DTL/TTL
CMOS 10V LEVEL TO DTL/TTL 5V LEVEL
COS/MOS
IN
0 = V
OL
5V = V
OH
CD4049
CD4049UB, CD4050B
