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SY100S302FC

Part # SY100S302FC
Description IC GATE OR/NOR QUINT 2IN 24-CPAK
Category IC
Availability In Stock
Qty 230
Qty Price
1 - 11 $22.03217
12 - 28 $17.52559
29 - 60 $16.52413
61 - 130 $15.35576
131 + $13.68665
Manufacturer Available Qty
SYNERGY
Date Code: 03
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Max. propagation delay of 700ps
IEE min. of –45mA
Industry standard 100K ECL levels
Extended supply voltage option:
VEE = –4.2V to –5.5V
Voltage and temperature compensation for
improved noise immunity
Internal 75K input pull-down resistors
50% faster than Fairchild 300K
Function and pinout compatible with Fairchild F100K
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S302 offers five 2-input OR/NOR gates
designed for use in high-performance ECL systems. The
five gates are controlled by a common Enable signal. All
inputs have 75K pull-down resistors and all outputs are
buffered.
SY100S302
QUINT 2-INPUT
OR/NOR GATE
Oc
Oc
VCCA
VCC
Od
VCC
D1b
VEE
E
D
2b
D1c
VEES
4
3
2
1
28
27
12
13
14
15
16
17
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
O
dD2c
2618
25
5
D2a
D1a
Oa
VEES
Oa
Ob
Ob
D1e
VEES
D2d
D2e
D1d
Oe
Oe
BLOCK DIAGRAM
Oa
Oa
D1a
D2a
Ob
Ob
D1b
D2b
Oc
Oc
D1c
D2c
Od
Od
D1d
D2d
Oe
Oe
D1e
D2e
E
FEATURES
PIN CONFIGURATIONS
Rev.: G Amendment: /0
Issue Date: July, 1999
D
2c
D
1c
E
V
EE
D
2b
D
1b
D
2a
D
1a
O
a
O
a
O
b
O
b
D
1d
D
1e
O
e
D
2d
O
e
D
2e
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
V
CC
V
CCA
O
d
O
c
O
d
O
c
Pin Function
Dna – Dne Data Inputs (n-1...5)
E Enable Input
Oa – Oe Data Outputs
Oa – Oe Complementary Data Outputs
VEES VEE Substrate
V
CCA VCCO for ECL Outputs
PIN NAMES
1
2
SY100S302
Micrel
D1X D2X E OX OX
L LLL H
LLHHL
LHLHL
L HHH L
HLLHL
HLHHL
HHLHL
H HHH L
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
TRUTH TABLE
(1)
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
IIH Input HIGH Current, All Inputs 200 µAVIN = VIH (Max.)
I
EE Power Supply Current –45 –28 –21 mA Inputs Open
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
t
PLH Propagation Delay 300 750 300 750 300 750 ps
tPHL Data to Output
t
PLH Propogation Delay 250 950 250 950 250 950 ps
tPHL Enable to Output
t
TLH Transition Time 300 900 300 900 300 900 ps
tTHL 20% to 80%, 80% to 20%
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
t
PLH Propagation Delay 250 700 250 700 250 700 ps
tPHL Data to Output
t
PLH Propogation Delay 250 900 250 900 250 900 ps
tPHL Enable to Output
t
TLH Transition Time 300 900 300 900 300 900 ps
tTHL 20% to 80%, 80% to 20%
3
SY100S302
Micrel
Ordering Package Operating
Code Type Range
SY100S302FC F24-1 Commercial
SY100S302JC J28-1 Commercial
SY100S302JCTR J28-1 Commercial
TIMING DIAGRAM
Propagation Delay and Transition Times
PRODUCT ORDERING CODE
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
20%
80%
OUTPUT
INPUT
50%
t
PLH
t
PHL
50%
20%
80%
50%
t
PHL
t
PLH
t
TLH
t
THL
TRUE
COMPLEMENT
0.7 ± 0.1 ns0.7 ± 0.1 ns
0.95V
1.69V
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