Product Specification
PE97022
Page 3 of 14
Document No. 70-0235-04 │ www.psemi.com
©2007-2008 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Pin Descriptions (continued)
Pin No. Pin Name Interface Mode Type Description
14
Sdata Serial Input Binary serial data input. Input data entered MSB first.
D
5
Parallel Input Parallel data bus bit5.
M
5
Direct Input M Counter bit5.
15
Sclk Serial Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
D
6
Parallel Input Parallel data bus bit6.
M
6
Direct Input M Counter bit6.
16
FSELS Serial Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
D
7
Parallel Input Parallel data bus bit7 (MSB).
Pre_en
Direct Input Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
17 GND ALL Ground.
18
FSELP Parallel Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A
0
Direct Input A Counter bit0 (LSB).
19
E_WR
Serial Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Parallel Input
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A
1
Direct Input A Counter bit1.
20
M2_WR Parallel Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A
2
Direct Input A Counter bit2.
21
Smode Serial, Parallel Input
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A
3
Direct Input A Counter bit3 (MSB).
22
Bmode
ALL Input
Selects direct interface mode (Bmode=1).
23 V
DD
ALL (Note 1) Same as pin 1.
24 M1_WR Parallel Input
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_W R.
25 A_WR Parallel Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
26 Hop_WR Serial, Parallel Input
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
27 F
in
ALL Input Prescaler input from the VCO. 3.5 GHz max frequency.
28
F
in
ALL Input
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
29 GND ALL Ground.
30 f
p
ALL Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
