Name: SN74LVC1G11DCKR
SKU: SN74LVC1G11DCKR
Price: 0.11955 USD
Availability: OutOfStock



   

SCES487B − SEPTEMBER 2003 − REVISED FEBRUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Available in the Texas Instruments

NanoStar and NanoFree Packages

D Supports 5-V V

Operation

D Inputs Accept Voltages to 5.5 V

D Max t

of 4.1 ns at 3.3 V

D Low Power Consumption, 10-µA Max I

D ±24-mA Output Drive at 3.3 V

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74LVC1G11 performs the Boolean function

Y + A • B • CorY+ A

) B ) C

in positive logic.

NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

NanoStar − WCSP (DSBGA)

0.23-mm Large Bump − YEP

Tape and reel

SN74LVC1G11YEPR

_ _ _C3_

−40°C to 85°C

NanoFree − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

Tape and reel

SN74LVC1G11YZPR

_ _ _C3_

SOT (SOT-23) − DBV Tape and reel SN74LVC1G11DBVR C11_

SOT (SC-70) − DCK Tape and reel SN74LVC1G11DCKR C3_

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

‡

DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one

following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition

(1 = SnPb,

• = Pb-free).

NanoStar and NanoFree are trademarks of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DBV OR DCK PACKAGE

(TOP VIEW)

GND

YEP OR YZP PACKAGE

(BOTTOM VIEW)

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   

SCES487B − SEPTEMBER 2003 − REVISED FEBRUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUT

A B C

OUTPUT

H H H H

L XX L

X LX L

X X L L

logic diagram (positive logic)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

−0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, V

(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or low state, V

(see Notes 1 and 2) −0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 3): DBV package 165°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DCK package 259°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

YEP/YZP package 123°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of V

is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51-7.



   

SCES487B − SEPTEMBER 2003 − REVISED FEBRUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN MAX UNIT

Supply voltage

Operating 1.65 5.5

Supply voltage

Data retention only

1.5

= 1.65 V to 1.95 V 0.65 × V

High-level input voltage

= 2.3 V to 2.7 V 1.7

High-level input voltage

= 3 V to 3.6 V

= 4.5 V to 5.5 V 0.7 × V

= 1.65 V to 1.95 V 0.35 × V

Low-level input voltage

= 2.3 V to 2.7 V 0.7

Low-level input voltage

= 3 V to 3.6 V

0.8

= 4.5 V to 5.5 V 0.3 × V

Input voltage 0 5.5 V

Output voltage 0 V

= 1.65 V −4

= 2.3 V −8

High-level output current

= 3 V

−16

High-level output current

= 3 V

−24

= 4.5 V −32

= 1.65 V 4

= 2.3 V 8

Low-level output current

= 3 V

Low-level output current

= 3 V

= 4.5 V 32

= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20

∆t/∆v Input transition rise or fall rate

= 3.3 V ± 0.3 V

ns/V

∆t/∆v

Input transition rise or fall rate

= 5 V ± 0.5 V 10

ns/V

Operating free-air temperature −40 85 °C

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Part #	SN74LVC1G11DCKR
Description	SINGLE 3-INPUT POSITIVE-AND GATE - Cut TR (SOS)
Category	IC
Availability	Out of Stock
Qty	0

SN74LVC1G11DCKR

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