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ZL2005PALRFT

Part # ZL2005PALRFT
Description IC REG CNTRLR BUCK PWM 36-QFN
Category IC
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Zilker Labs
Date Code: 1010
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

28
FN6849.3
December 16, 2011
method is preferred if the user does not desire to use or
does not have access to the I
2
C/SMBus interface and
the desired threshold value is contained in Table 23.
Table 23. Current Limit Threshold Voltage
Settings
The current limit threshold can be set via the I
2
C/
SMBus interface. Please refer to Application Note
AN2013 for further details on setting current limit
parameters.
5.10 Loop Compensation
The ZL2005P operates as a voltage-mode synchro-
nous buck controller with a fixed frequency PWM
scheme. Alth
ough the ZL2005P uses a digital control
loop, it operates much like a traditional analog PWM
controller. See Figure 19 for a simplified block dia-
gram of the ZL2005P control loop, which differs from
an ana
log control loop by the constants in the PWM
and compensation blocks. As in the analog controller
case, the compensation block compares the output
voltage to the desired voltage reference and compen-
sation zeros are added to keep the loop stable. The
resulting integrated error signal is used to drive the
PWM
logic, converting the error signal into a duty
cycle value to drive the external MOSFETs.
Figure 19. Control Loop Block Diagram
In the ZL2005P, the compensation zeros are set by
co
nfiguring the FC0 pin or via the I
2
C/SMBus inter-
face once the user has calculated the required
settings.
Most applications can be served by using the pin-strap
compensation settings listed in Table 24. These set-
tings will yield a conservative crossover frequency.
The
parameters of the feedback compensation can also
be set using the I
2
C/SMBus interface. A sofware
(CompZL
TM)
is also available from Zilker Labs to cal-
culate automatically the compensation parameters.
FC1 pin is not used in the ZL2005P.
Table 24. Pin-Strap Setting for Loop
Compen
sation
5.11 Non-Linear Response Settings
The ZL2005P incorporates a non-linear response
(NLR) loop that decreases the response time and the
output voltage deviation in the event of a sudden out-
put load current step. The NLR loop incorporates a
se
condary error signal processing path that bypasses
the primary error loop when the output begins to tran-
sition outside of the standard regulation limits. T
his
scheme results in a higher equivalent loop bandwidth
than is possible using a traditional linear loop.
When a load current step fu
nction imposed on the out-
put causes the output voltage to drop below the lower
regulat
ion limit, the NLR circuitry will force a positive
correction signal that will turn on the upper MOSFET
and quickly force the output to increase. A negative
load step will cause the NLR circuitry to force a nega-
V
LIM
R
LIM0
V
LIM
R
LIM0
0 mV
10 kΩ
55 mV
28.7 kΩ
5 mV
11 kΩ
60 mV
31.6 kΩ
10 mV
12.1 kΩ
65 mV
34.8 kΩ
15 mV
13.3 kΩ
70 mV
38.3 kΩ
20 mV
14.7 kΩ
75 mV
42.2 kΩ
25 mV
16.2 kΩ
80 mV
46.4 kΩ
30 mV
17.8 kΩ
85 mV
51.1 kΩ
35 mV
19.6 kΩ
90 mV
56.2 kΩ
40 mV
21.5 kΩ
95 mV
61.9 kΩ
45 mV
23.7 kΩ
100 mV
68.1 kΩ
50 mV
26.1 kΩ
FC0 Pin Description
HIGH High Q, Low Bandwidth
OPEN Real zeros, High Bandwidth
LOW Low Q, Low Bandwidth
D
1-D
V
IN
V
OUT
L
C
DPWM
R
C
Compensation
R
O
ZL2005P
29
FN6849.3
December 16, 2011
tive correction signal that will turn on the lower MOS-
FET and quickly force the output to decrease.
5.12 Efficiency Optimized Driver Dead-
time Control
The ZL2005P utilizes a closed loop algorithm to opti-
mize the dead-time applied between the gate drive sig-
nals for the top and bottom FETs. In a synchronous
buck converter, the MOSFET drive circuitry must be
designed such that the top and bottom MOSFETs are
never in the conducting state at the same time. (Poten
-
tially damaging currents flow in the circuit if both top
and bottom MOSFETs are simultaneously on for peri
-
ods of time exceeding a few nanoseconds.) Con-
versely, long periods of time in which both MOSFETs
are off reduce overall circuit efficiency by allowing
current to flow in their parasitic body diodes.
It is therefore advantageous to minimize this dead-
time to provide optimum circuit efficiency. In the first
order model of a buck converter, the duty cycle is
determined by the equation:
D = V
OUT
/ V
IN
-------------------- (29)
However, non-idealities exist that cause the real duty
cycle to extend beyond the ideal. Deadtime is one of
those non-idealities that can be manipulated to
improve efficiency. The ZL2005P has an internal algo
-
rithm that constantly adjusts deadtime non-overlap to
minimize duty cycle, thus maximizing efficiency. This
circuit will null out deadtime differences due to com
-
ponent variation, temperature and loading effects.
This algorithm is independent of application circuit
parameters such as MOSFET type, gate driver delays,
rise and fall times and circuit layout. In addition, it
does not require drive or MOSFET voltage or current
waveform measurements.
ZL2005P
30
FN6849.3
December 16, 2011
6 Power Management Functional Description
6.1 Input Undervoltage Lockout (UVLO)
Standard Mode
The input undervoltage lockout (UVLO) prevents the
ZL2005P from operating when the input falls below a
preset threshold, indicating the input supply is out of its
specified range. The UVLO threshold (V
UVLO
) can be
set between 2.85 V and 16 V using the UVLO pin. The
simplest implementation is to connect the UVLO pin as
shown in Table 25. If the UVLO pin is left uncon-
nected, the UVLO threshold will default to 4.5 V.
Table 25. UVLO Threshold Settings
LOW 3 V
OPEN 4.5 V
HIGH 10.8 V
If the desired UVLO threshold is not one of the listed
choice
s, the user can configure a threshold between
2.85 V and 16 V by connecting a resistor between the
UVLO pin and GND by selecting the appropriate
resistor from Table 26.
Table 26. UVLO Resistor Values
2.85 V 17.8 kΩ 7.42 V 46.4 kΩ
3.14 V 19.6 kΩ 8.18 V 51.1 kΩ
3.44 V 21.5 kΩ 8.99 V 56.2 kΩ
3.79 V 23.7 kΩ 9.9 V 61.9 kΩ
4.18 V 26.1 kΩ 10.9 V 68.1 kΩ
4.59 V 28.7 kΩ 12 V 75 kΩ
5.06 V 31.6 kΩ 13.2 V 82.5 kΩ
5.57 V 34.8 kΩ 14.54 V 90.9 kΩ
6.13 V 38.3 kΩ 16 V 100 kΩ
6.75 V 42.2 kΩ
V
UVLO
can also be set to any value between 2.85 V
and 16 V via I
2
C/SMBus.
Once an input undervoltage fault condition
occurs, the
device can respond in a number of ways as follows:
1. Continue operating wit
hout interruption.
2. Continue operating for a given delay time, fol-
lowed by shutdown if the fault still persists at the
end of the delay period. The devi
ce will remain in
shutdown until permitted to restart.
3. Initiate an immediate shutdown until the fault has
been
cleared. The user can select a specific num-
ber of retry attempts.
The default response from a
UVLO fault is an imme-
diate shutdown of the device. The
device will continu-
ously check for the presence of the fault condition. If
the
fault condition is no longer present, the ZL2005P
will be re-enabled.
Please refer to Application Note AN2013 for details
on
how to configure the UVLO threshold or to select
specific UVLO fault response options via the I
2
C/
SMBus interface.
6.2 Output Overvoltage Protection
The ZL2005P offers an internal output overvoltage
protection circuit that can be used to protect sensitive
load circuitry from being subjected to a voltage higher
than its prescribed limits. This feature is especially
useful in protecting expensive processors, FPGAs, and
ASICs from excessive voltages.
A hardware comparator is used to compare the actual
ou
tput voltage (seen at the VSEN pin) to a threshold set
to 15% higher than the target output voltage by default.
If the voltage at the VSEN pin exceeds this upper
threshold level, the PG pin will de-assert. The device
can then respond in a number of ways as follows:
1. Initiate an immediate shutdown until the fault has
been
cleared. The user can select a specific num-
ber of retry attempts.
2. Turn off the high-side MOSFET and turn on the
low-side MOSFET
. The low-side MOSFET
remains ON until the device attempts a restart.
The default response from an overvoltage fault
is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condi-
tion. If the fault condition is no
longer present, the
ZL2005P will be re-enabled.
Please refer to Application Note AN2013 for details
on how to sele
ct specific overvoltage fault response
options via the I
2
C/SMBus interface.
Pin Setting UVLO Threshold
UVLO R
UVLO
UVLO R
UVLO
ZL2005P
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