21
FN6849.3
December 16, 2011
Figure 16. SYNC Pin Configurations
Configuration A: SYNC OUTPUT
When the SYNC pin is configured as an output (CFG
pin is tied HIGH), the device will operate from its
internal oscillator and will drive the resulting internal
oscillator signal (preset to 400 kHz) onto the SYNC
pin so other devices can be synchronized to it. The
SYNC pin will not be checked for an incoming clock
signal while in this configuration.
Configuration B: SYNC INPUT
When the SYNC pin is configured as an input (CFG
pin is tied LOW), the device will automatically check
for a clock signal on the SYNC pin each time EN is
asserted. The ZL2005P’s oscillator will then synchro
-
nize with the rising edge of external clock.
The incoming clock signal must be in the range of 200
kHz to 1.4 MHz and must be stable when the enable
pin is asserted. The clock signal must also exhibit the
necessary performance requirements (see
Table 3). In
the event of a loss of the external clock signal, the out-
put voltage may show transient over/undershoot.
If this happens, the ZL2005P will turn off the power
FETs (QH and QL in Figure
4) typically within 10 μS.
Users are discouraged from removing an external
SYNC clock while the ZL2005P is operating with
Enable asserted.
Configuration C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode
(CFG pin is left OPEN), the device will automatically
check for a clock signal on the SYNC pin after enable
is asserted.
If a clock signal is present, The ZL2005P’s oscillator
will then synchronize the rising edge of the external
clock. Refer to SYNC INPUT description.
If no incoming clock signal is present, the ZL2005P
will configure the switching frequency according to
the state of the SYNC pin as listed in
Table 16. In this
mode, the ZL2005P will only read the SYNC pin con-
nection during the start-up sequence. Changes to
SYNC pin connections will not affect f
SW
until the
power (VDD) is cycled off and on.
Table 16. Switching Frequency Selection
If the user wishes to run the ZL2005P at a frequency
other than those listed in
Table 16, the switching fre-
quency can be set using an external resistor, R
SYNC
,
connected between SYNC and SGND using
Table 17.
ZL
Logic
high
CFG
SYNC
200 kHz – 1.4 MHz
ZL
CFG
SYNC
200 kHz – 1.4 MHz
ZL
N/C
CFG
SYNC
200 kHz – 1.4 MHz
A) SYNC = output
B) SYNC = input
ZL
N/C
CFG
SYNC
ZL
R
SYNC
N/C
CFG
SYNC
Logic
high
Logic
low
Open
C) SYNC = Auto Detect
OR OR
SYNC Pin Setting Frequency
LOW 200 kHz
OPEN 400 kHz
HIGH 1 MHz
Resistor See Table 17
ZL2005P
