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ZL2005PALRFT

Part # ZL2005PALRFT
Description IC REG CNTRLR BUCK PWM 36-QFN
Category IC
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Zilker Labs
Date Code: 1010
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Zilker Labs
Date Code: 1010
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

16
FN6849.3
December 16, 2011
The standard method for adjusting output voltage used
in a POLA module is defined by the below equation:
R
set
= 10kΩ x 0.69V/(V
OUT
– 0.69V) – 1.43kΩ
Rset is an external resistor.
VADJ
ZL2005P
10
kOhm
MODULE
R
SET
-
+
1.43
kOhm
R
SET
0.69V
10
kOhm
V
OUT
POLA Module
Figure 11. Output Voltage Resistor Setting
POLA - ZL2005P
To stay compatible with existing methods for
adjusting
output voltage, the module manufacturer can add a 10
kΩ resistor on the module.
R
VADJ
= R
SET
+10 kΩ
By adding this additional resistor
, the resistor values
shown in Table 8 can be used to set the output
voltage
of a ZL2005P module. These values are close to the
a
nalog POLA values and are compatible with the pin-
strap resistor detection methodology of the ZL2005P.
DOSA Voltage Trim Method
For DOSA output voltage selection, a 8.66 kΩ re
sistor
needs to be used in place of the 10 kΩ
resistor. This
will allow setting the output voltage with resistor val-
ues close to the DOSA equation result:
R
set
= 6900/(V
OUT
– 0.69V).
Table 9. Resistors for Setting DOSA Output
V
oltage with VADJ
0.700V 156 / 160 / 170 0.991V 22.71 / 22.94 / 23.17
0.752V 111.22 / 112.34 / 113.46 1.000V 19.84 / 20.04 / 20.24
0.758V 100.33 / 101.34 / 102.35 1.100V 17.27 / 17.44 / 17.61
0.765V 90.43 / 91.34 / 92.25 1.158V 14.89 / 15.04 / 15.19
0.772V 81.42 / 82.24 / 83.06 1.200V 12.71 / 12.84 / 12.97
0.790V 65.68 / 73.84 / 74.58 1.250V 10.83 / 10.94 / 11.05
0.800V 58.85 / 59.44 / 60.03 1.500V 9.05 / 9.14 / 9.23
0.821V 52.71 / 53.24 / 53.77 1.669V 7.46 / 7.54 / 7.62
0.848V 42.02 / 42.44 / 42.86 1.800V 5.98 / 6.04 / 6.10
0.880V 37.36 / 37.74 / 38.12 2.295V 4.59 / 4.64 / 4.69
0.899V 33.20 / 33.54 / 33.88 2.506V 3.41 / 3.44 / 3.47
0.919V 29.34 / 29.64 / 29.94 3.300V 2.32 / 2.34 / 2.36
0.965V 25.88 / 26.14 / 26.40 5.000V 1.33 / 1.34 / 1.35
UVLO (POLA Mode)
In POLA mode 1 and 2, undervoltage threshold
(UVLO)
is set following POLA standard methodol-
ogy.
In the POLA standard, a resistor on the UVLO pin sets
the corresponding voltage value.
For a module supplier, a 1.5 kΩ 1% pull-up resistor
from EN to UVLO is required to be compatible with
the POLA Inhibit/UVLO features (Figure 12). EN
must be driven by an open
collector/drain driver, and
will default to Enabled unless pulled low. The driver
must remain open after a transition for a minimum of 1
ms to allow the measurement of the resistor on the
UVLO pin.
By default UVLO is set to 4.5V.
Table 8. Resistors for Setting POLA Output
V
oltage with VADJ
V
OUT
R
SET
(kΩ)
Min / Typ / Max
V
OUT
R
SET
(kΩ)
Min / Typ / Max
0.700V 155 / 159 / 169 0.991V 21.38 / 21.6 / 21.82
0.752V 109.89 / 111 / 112.11 1.000V 18.51 / 18.7 / 18.89
0.758V 99 / 100 / 101 1.100V 15.94 / 16.1 / 16.26
0.765V 89.1 / 90 / 90.9 1.158V 13.56 / 13.7 / 13.84
0.772V 80.09 / 80.9 / 81.71 1.200V 11.39 / 11.5 / 11.62
0.790V 64.35 / 72.5 / 73.23 1.250V 9.5 / 9.6 / 9.7
0.800V 57.52 / 58.1 / 58.68 1.500V 7.72 / 7.8 / 7.88
0.821V 51.38 / 51.9 / 52.42 1.669V 6.14 / 6.2 / 6.26
0.848V 40.69 / 41.1 / 41.51 1.800V 4.65 / 4.7 / 4.75
0.880V 36.04 / 36.4 / 36.76 2.295V 3.27 / 3.3 / 3.33
0.899V 31.88 / 32.2 / 32.52 2.506V 2.08 / 2.1 / 2.12
0.919V 28.02 / 28.3 / 28.58 3.300V 0.99 / 1 / 1.01
0.965V 24.55 / 24.8 / 25.05 5.000V 0 / 0 / 0.05
V
OUT
R
SET
(kΩ)
Min / Typ / Max
V
OUT
R
SET
(kΩ)
Min / Typ / Max
ZL2005P
17
FN6849.3
December 16, 2011
Figure 12. UVLO Circuit
Figure 12 shows how to select UVLO based on an
external resistor R
SET
.
R
UVLO
maps the POLA equation to set the UVLO
threshold:
R
UVLO
= (9690 - (137*V
IN
))/(137*V
IN
-585) in kΩ
Table 10 shows a chart of standard resistor values for
R
UVLO
:
Table 10. Resistors for Setting UVLO with
R
UVLO
4.3V 162 kΩ 6.20V 38.3 kΩ
4.5V 121 kΩ 6.60V 28.7 kΩ
4.87V 110 kΩ 6.96V 23.7 kΩ
4.93V 100 kΩ 7.22V 21.5 kΩ
4.99V 90.9 kΩ 7.50V 19.6 kΩ
5.07V 82.5 kΩ 7.81V 17.8 kΩ
5.15V 75.0 kΩ 8.13V 16.2 kΩ
5.23V 68.1 kΩ 8.50V 14.7 kΩ
5.33V 61.9 kΩ 8.92V 13.3 kΩ
5.43V 56.2 kΩ 9.34V 12.1 kΩ
5.55V 51.1 kΩ 9.81V 11.0 kΩ
5.67V 46.4 kΩ 10.86V 9.09 kΩ
5.81V 42.2 kΩ 11.46V 8.25 kΩ
For a POLA module, the Inhibit feature is combined
with UVL
O.
Figure 13. INHIBIT Circuit
Figure 13 shows the typical application of the Inhibit
function. The inhibit input has its own
internal pull-up.
An open-drain transistor is recommended for control.
Flexible pin
When POLA_VADJ_CONFIG is set to mode 2, the
ZL2005P uses the V
ADJ pin for output voltage setting
and it also disables the SYNC pin. In this mode, the
ZL2005P is not checking the SYNC pin for synchroni-
zation to an external signal. Otherwise the resistor
me
asurement may not be accurate. This configuration
allows a module supplier to connect both VADJ and
SYNC pin to a common pin on the module (Flex pin).
A single module pin can then be used for one or the
other function.
In this mode UVLO will also
follow the POLA
method.
SYNC VADJ
ZL2005P
10kO
MODULE
FLEX PIN
Figure 14. Output Voltage Resistor Setting
Example
UVLO
R
UVLO
in series with
1.5 kΩ
resistor
UVLO
R
UVLO
in series with
1.5 kΩ
resistor
UVLO
ZL2005P
1.5 kOhm
MODULE
RUVLO
Inhibit/
UVLO
EN
UVLO
ZL2005P
1.5 kOhm
MODULE
RUVLO
Inhibit/
UVLO
EN
1 = Inhibit
Q1
ZL2005P
18
FN6849.3
December 16, 2011
5.4 Start-up Procedure
The ZL2005P follows a specific internal start-up pro-
cedure after power is applied to the VDD pin. Table 11
describes the start-up sequence.
If the device is to be synchro
nized to an external clock
source, the clock must be stable prior to asserting the
EN pin. The device requires approximately 10-20 ms
to check for specific values stored in its internal mem-
ory.
If the user has stored values in memory, those values
will
be loaded. The device will then check the status of
all multi-mode pins and load the values associated
with the pin settings.
Once this process is completed, the device is ready to
ac
cept commands via the I
2
C/SMBus interface and the
device is ready to be enabled. Once enabled, the
device requires approximately 6 ms before its output
voltage may be allowed to start its ramp-up process. If
a soft start delay period less than 6 ms has been con-
figured (using the DLY (0,1) pins), the device will
default
to a 6 ms delay period. If a delay period of 6
ms or higher is configured, the device will wait for the
configured delay period before starting to ramp its out-
put.
After the delay period has expired, the output will
begin to ra
mp towards its target voltage according to
the pre-configured soft-start ramp time.
Table 11. ZL2005P Start-up Sequence
1 Power Applied Input voltage is applied to the ZL2005P’s VDD pin
Depends on input supply
ramp time
2
Internal Memory
Check
The device will check for values stored in its internal
memory
. This step is also performed after a Restore
command.
Approx 10-20 ms (device
will
ignore an enable signal
or PMBus traffic during this
period)
3
Multi-mode
Pi
n Check
The device loads values configured by multi-mode
pins.
4 Device Ready The device is ready to accept an ENABLE signal.
5 Pre-ramp Delay
The device requires approximately 6 ms following an
e
nable signal and prior to ramping its output.
Additional pre-ramp delay may be configured using
the Delay pins.
Approx. 6 ms
Step # Step Name Description Time Duration
ZL2005P
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