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ZL2005PALRFT

Part # ZL2005PALRFT
Description IC REG CNTRLR BUCK PWM 36-QFN
Category IC
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Zilker Labs
Date Code: 1010
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Zilker Labs
Date Code: 1010
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Zilker Labs
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

13
FN6849.3
December 16, 2011
Figure 8. Pin-strap and Resistor Setting
Examples
Pin-strap Settings: This is the simplest implementa-
tion method, as no external components are required.
Using this method, each pin can take on one of three
possible states: GND, OPEN, or HIGH. These pins
can be connected to the VR or V25 pins for logic
HIGH settings, as either pin provides a regulated volt
-
age greater than 2V. Using a single pin, the user can
select one of three settings, and using two pins, the
user can select one of nine settings.
Resistor Settings: This method allows a greater range
of adjustability when connecting a finite valued resis
-
tor (in a specified range) between the multi-mode pin
and SGND. Standard 1% resistor values are used, and
only every fourth E96 resistor value is used so that the
device can reliably recognize the value of resistance
connected to the pin while eliminating the errors asso
-
ciated with the resistor accuracy. A total of 25 unique
selections are available using a single resistor.
I
2
C/SMBus Settings: Almost any ZL2005P function
can be configured via the I
2
C/SMBus interface using
standard PMBus commands. Additionally, any value
that has been configured using the pin-strap or resistor
setting methods can also be re-configured and/or veri
-
fied via the I
2
C/SMBus. See Application Note
AN2013 for details.
The SMBus device address and VOUT_MAX are the
only parameters that must be set by external pins. All
other device parameters can be set via the I
2
C/SMBus.
the device address is set using the SA0 and SA1 pins.
The VOUT_MAX is determined as 10% greater than
the voltage set by the V0/V1 pins or VADJ pin.
ZL
Multi-mode Pin
ZL
R
SET
Logic
high
Logic
low
Open
Pin-strap
Settings
Resistor
Settings
Multi-mode Pin
ZL2005P
14
FN6849.3
December 16, 2011
5 Power Conversion Functional Description
5.1 Internal Bias Regulators and Input
Supply Connections
The ZL2005P employs two internal low dropout
(LDO) regulators to supply bias voltages for internal
circuitry, allowing it to operate from a single input
supply. The internal bias regulators are as follows:
VR: The VR LDO provides a regulated 5V bias supply
for
the MOSFET driver circuits. It is powered
from the VDD pin and can supply up to 100 mA
output current. A 4.7 µF filter capacitor is
required at the VR pin.
V25: The V25 LDO provides a regulated 2.5V bias
supply for the main controller circuitry
. It is
powered from an internal 5V node and can sup-
ply up to 50 mA output current. A 10 µF filter
capac
itor is required at the V25 pin.
Note:
The internal bias regulators are designed for
powering internal circuitry only. Do not attach exter-
nal loads to any of these pins. The multi-mode pins
ma
y be connected to the VR or V25 pins for logic
HIGH settings.
When the input supply (V
DD
) is higher than 5.5V, the
VR pin should not be connected to any other pin. It
should only have a filter capacitor attached as shown
in Figure 9. Due to the dropout voltage associated with
the VR bias regulator, the VDD pin must be connected
to the V
R pin for designs operating from a VDD sup-
ply from 3.0V to 5.5V. Figure 9 illustrates the required
connections for both cases. F
or input supplies between
4.5V and 5.5V, either method can be used.
Figure 9. Input Supply Connections
5.2 High-side Driver Boost Circuit
The gate drive voltage for the upper MOSFET driver
is generated by a floating bootstrap capacitor, CB (see
Figure 3). When the lower MOSFET (QL) is turned
on, the SW node is pulled to
ground and the capacitor
is charged from the internal VR bias regulator through
diode DB. When QL turns off and the upper MOSFET
(QH) turns on, the SW node is pulled up to V
DD
and
the voltage on the BST pin is boosted approximately
5V above V
IN
to provide the necessary voltage for the
high-side driver. A Schottky diode should be used for
DB to maximize the high-side drive voltage.
5.3 Output Voltage Selection
Standard Mode (ZL2005)
The output voltage may be set to any voltage between
0.
6V and 5.0V provided that the input voltage is
higher than the desired output voltage by an amount
sufficient to prevent the device from exceeding its
maximum duty cycle specification. By connecting the
V0 and V1 pins to logic high, logic low, or leaving
them floating, V
OUT
can be set to any of nine standard
voltages as shown in Table 6.
Table 6.
Pin-strap Output Voltage Settings
If an output voltage other than those in Table 6 is
desired, the resistor setting method can
be used. Using
this method, resistors R0 and R1 are selected to pro-
duce a specific voltage between 0.6V and 5.0V in 10
mV steps.
Resistor R1 provides a coarse setting and
R0 a fine adjustment, thus eliminating the additional
errors associated with using two 1% resistors in a stan-
dard analog implementation (this ty
pically adds 1.4%
error using two 1% resistors).
To set V
OUT
using resistors, follow the steps below to
calculate an index value and then use Table 7 to select
the resistor that corresponds to the calculated index
value as
follows:
V0
LOW OPEN HIGH
V1
LOW
0.6V 0.8V 1.0V
OPEN
1.2V 1.5V 1.8V
HIGH
2.5V 3.3V 5.0V
ZL2005P
15
FN6849.3
December 16, 2011
1. Calculate Index1:
Index1 = 4 x V
OUT
2. Round the result down to the nearest whole num-
ber.
3. Select the value for R1 from Table 7 using the
Index1 rounded value from step 2.
4. Calculate Index0 using equation
Index0 = 100 x V
OUT
- 25 x Index1...
5. Select the value for R0 from Table 7 using Index0
from step 4.
Example:
For V
OUT
= 1.33V:
Index1 = 4 x 1.33V = 5.32 (5);
From Table 7, using Index = 5
R1 = 16.2 kΩ
Index0 = (100 x 1.33V) - (25 x 5) = 8;
From Table 7; R0 = 21.5 kΩ
Figure 10. Output Voltage Resistor Setting
The output voltage may also be set to any value
between 0.6V and 5.0V using the I
2
C/SMBus inter-
face. The maximum voltage that can be set is limited
to 110% of the pin-strap value. See Application Note
AN2013 for details.
POLA/DOSA Trim Method
The output voltage can also be set using the VADJ pin
to map the standard analog resistor method. This mode
is activated by setting the PMBus private command
POLA_VADJ_CONFIG to 1.
The POLA/DOSA mode can also be set up by pinstrap
using a resistor on V0.
A 110 kΩ resistor on V0 will set to POLA mode 1.
A 120 kΩ resistor on V0 will set to POLA mode 2.
In POLA mode 1 and 2, V0 and V1 pins are inactive,
and the ZL2005P uses the following table to set the
output voltage with the VADJ pin.
Table 7. Resistors for Setting Output Voltage
Index R0 or R1 Index R0 or R1
010 kΩ 13 34.8 kΩ
111 kΩ 14 38.3 kΩ
212.1 kΩ 15 42.2 kΩ
313.3 kΩ 16 46.4 kΩ
414.7 kΩ 17 51.1 kΩ
516.2 kΩ 18 56.2 kΩ
617.8 kΩ 19 61.9 kΩ
719.6 kΩ 20 68.1 kΩ
821.5 kΩ 21 75 kΩ
923.7 kΩ 22 82.5 kΩ
10 26.1 kΩ 23 90.9 kΩ
11 28.7 kΩ 24 100 kΩ
12 31.6 kΩ
ZL2005P
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