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ZL2005PALRFT

Part # ZL2005PALRFT
Description IC REG CNTRLR BUCK PWM 36-QFN
Category IC
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Zilker Labs
Date Code: 1010
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Zilker Labs
Date Code: 1010
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Zilker Labs
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

10
FN6849.3
December 16, 2011
4 ZL2005P Overview
4.1 Digital-DC Architecture
The ZL2005P is an innovative mixed-signal power
conversion and power management IC based on Zilker
Labs’ patented Digital-DC technology that provides
an integrated, high performance step-down converter
for a wide variety of power supply applications. Its
unique digital PWM loop utilizes an innovative
mixed-signal topology to enable precise control of the
power conversion process with no software required,
resulting in a very flexible device that is also easy to
use. An extensive set of power management functions
is fully integrated and can be configured using simple
pin connections or via the I
2
C/SMBus hardware inter-
face using standard PMBus commands. The user con-
figuration can be saved in an on-chip non-volatile
memory (NVM), allowing ultimate flexibility.
Once enabled, the ZL2005P is immediately ready to
regulate power and perform power management tasks
with no programming required. The ZL2005P can be
configured by simply connecting its pins according to
the tables provided in this document. Advanced con-
figuration options and real-time configuration changes
are available via the I
2
C/SMBus interface if desired,
and continuous monitoring of multiple operating
parameters is possible with minimal interaction from a
host controller. Integrated sub-regulation circuitry
enables single supply operation from any supply
between 3V and 14V with no secondary bias supplies
needed.
Zilker Labs provides a comprehensive set of on-line
tools and application notes to assist with power supply
design and simulation. An evaluation board is also
available to help the user become familiar with the
device. This board can be evaluated as a stand-alone
platform using pin configuration settings. Addition
-
ally, a Windows™-based GUI is provided to enable
full configuration and monitoring capability via the
I
2
C/SMBus interface using an available computer and
the included USB cable.
Please refer to www.intersil.com/zilkerlabs/ for access
to the most up-to-date documentation and the Power-
Pilot
TM
simulation tool, or call your local Zilker Labs’
sales office to order an evaluation kit.
4.2 ZL2005 - ZL2005P
By default, the ZL2005P is configured as a standard
ZL2005 device.
The main differences between the ZL2005P config-
ured as a ZL2005P and the initial ZL2005 are the fol-
lowing:
TACH pin is not used (reserved for ZL2005P
POLA configuration).
VADJ pin to adjust voltage through an external
resistor, similar to POLA method.
Additional configuration option for Synchroniza-
tion.
DEFAULT STORE only
ZL2005P
11
FN6849.3
December 16, 2011
4.3 Power Conversion Overview
Figure 5. ZL2005P Detailed Block Diagram
The ZL2005P operates as a voltage-mode, synchro-
nous buck converter with a selectable, constant fre-
quency Pulse Width Modulator (PWM) contr
ol
scheme that uses external MOSFETs, inductor and
capacitors to perform power conversion.
Figure 6 illustrates the basic synchronous buck con-
verter topology showing the primary power train com-
ponents. This converter is also called a step-down
converter
, as the output voltage must always be lower
than the input voltage.
V
IN
V
OUT
GH
GL
ZL
SW
VR
BST
QH
QL
CB
DB
C
OUT
C
IN
L1
Figure 6. Synchronous Buck Converter
In its most simple configuration, the ZL2005P requires
two
external N-channel power MOSFETs, one for the
top control MOSFET (QH) and one for the bottom
synchronous MOSFET (QL). The amount of time that
QH is on as a fraction of the total switching period is
known as the duty cycle D, which is described by the
following equation:
D
VOUT
VIN
----------------
During time D, QH is on and V
IN
–V
OUT
is applied
across the inductor. The current ramps up as shown in
Figure 7.
Figure 7. Inductor Waveform
SYNC
GEN
ENPG V(0,1)
VDD
POWER MANAGEMENT
DIGITAL
COMPENSATOR
PLL
D-PWM
MOSFET
DRIVERS
NLR
ADC
ADC
MUX
COMMUNICATION
TEMP
SENSOR
VDD
XTEMP
VSEN
ISENA
ISENB
VSEN
SW
BST
V
OUT
SYNC
SALRT
SDA
SCL
SA(0,1)
SMBUS
REFCN DAC
INPUT VOLTAGE BUS
+
-
Σ
{
ADC
VTRK
GH
GL
VR LDO
VR
VADJ
NVM
VOLTAGE
(V)
Time
CURRENT (A)
V
IN
– V
OUT
0
-V
OUT
1-D
I
o
IL
pk
IL
v
D
ZL2005P
12
FN6849.3
December 16, 2011
When QH turns off (time 1-D), the current flowing in
the inductor must continue to flow from the ground up
through QL, during which the current ramps down.
Since the output capacitor C
OUT
exhibits a low imped-
ance at the switching frequency, the AC component of
the inductor current is filtered
from the output voltage
so the load sees nearly a DC voltage.
Typically, buck converters specify a maximum duty
cycle tha
t effectively limits the maximum output volt-
age that can be realized for a given
input voltage. This
duty cycle limit ensures that the low-side MOSFET is
allowed to turn on for a minimum amount of time dur-
ing each switching cycle, which enables the bootstrap
capac
itor (CB in Figure 6) to be charged up and pro-
vide adequate gate drive voltage
for the high-side
MOSFET. See Section 5.2, “High-side Driver Boost
Circuit,” for more details.
In general, the size of components L1 and C
OUT
as
well as the overall efficiency of the circuit are
inversely proportional to the switching frequency, f
SW
.
Therefore, the highest efficiency circuit may be real-
ized by switching the MOSFETs at the lowest possible
frequency;
however, this will result in the largest com-
ponent size. Conversely, the smallest
possible foot-
print may be realized by switching at the fastest
possible fre
quency but this gives a somewhat lower
efficiency. Each user should determine the optimal
combination of size and efficiency when determining
the switching frequency for each application.
The block diagram for the ZL2005P is illustrated in
Figure 5. In this circuit, the target output voltage is
regulated by connecting the VSEN pin directly to the
output regulat
ion point. The VSEN signal is then com-
pared to a reference voltage that has been set to the
de
sired output voltage level by the user. The error sig-
nal derived from this comparison is converted
to a dig-
ital value with a low-resolution analog t
o digital (A/D)
converter. The digital signal is applied to an adjustable
digital compensation filter, and the compensated sig-
nal is used to derive the appropriate PWM duty cyc
le
for driving the external MOSFETs in a way that pro-
duces the desired output.
The ZL2005P also incorporate
s a non-linear response
(NLR) loop to reduce the response time and output
deviation in response to a load transient. The ZL2005P
has an efficiency optimization circuit that continu-
ously monitors the power converter’s operating condi-
tions and adjusts the turn-on and turn-of
f timing of the
high-side and low-side MOSFETs to optimize the
overall efficiency of the power supply.
4.4 Power Management Overview
The ZL2005P incorporates a wide range of configu-
rable power management features that are simple to
implement with
no external components. Addition-
ally, the ZL2005P includes circuit protection features
that continuously
safeguard the load from damage due
to unexpected system faults. The ZL2005P can contin-
uously monitor input voltage, output voltage/current,
inte
rnal temperature, and the temperature of an exter-
nal thermal diode. A Power Goo
d output signal is pro-
vided to enable power-on reset functionality
for an
external processor.
All power management functions can be configured
using
either simple pin configuration techniques (Fig-
ure 8) or via the I
2
C/SMBus interface. Monitoring
parameters can be pre-configured to provide alerts for
specific conditions. See Application
Note AN2013 for
more details on SMBus monitoring.
4.5 Multi-mode Pins
In order to simplify circuit design, the ZL2005P incor-
porates patented multi-mode pins that allow the user
to
easily configure many aspects of the device without
requiring the user to program the IC. For the ZL2005P
only a few of the power management features can be
configured using these pins. The multi-mode pins can
respond to four different connections as shown in
Table 5. Any combination of connections is allowed
among the multi-mode pins. These pins
are sampled
when power is applied or by issuing a PMBus Restore
command (See Application Note AN2013).
Table 5. Multi-mode Pin Configuration
GND
(Logic low)
< 0.8 V
DC
OPEN
(N/C)
No connection
HIGH
(Log
ic high)
> 2.0 V
DC
Resistor to SGND Set by resistor value
Pin Tied To Value
ZL2005P
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