12
FN6849.3
December 16, 2011
When QH turns off (time 1-D), the current flowing in
the inductor must continue to flow from the ground up
through QL, during which the current ramps down.
Since the output capacitor C
OUT
exhibits a low imped-
ance at the switching frequency, the AC component of
the inductor current is filtered
from the output voltage
so the load sees nearly a DC voltage.
Typically, buck converters specify a maximum duty
cycle tha
t effectively limits the maximum output volt-
age that can be realized for a given
input voltage. This
duty cycle limit ensures that the low-side MOSFET is
allowed to turn on for a minimum amount of time dur-
ing each switching cycle, which enables the bootstrap
capac
itor (CB in Figure 6) to be charged up and pro-
vide adequate gate drive voltage
for the high-side
MOSFET. See Section 5.2, “High-side Driver Boost
Circuit,” for more details.
In general, the size of components L1 and C
OUT
as
well as the overall efficiency of the circuit are
inversely proportional to the switching frequency, f
SW
.
Therefore, the highest efficiency circuit may be real-
ized by switching the MOSFETs at the lowest possible
frequency;
however, this will result in the largest com-
ponent size. Conversely, the smallest
possible foot-
print may be realized by switching at the fastest
possible fre
quency but this gives a somewhat lower
efficiency. Each user should determine the optimal
combination of size and efficiency when determining
the switching frequency for each application.
The block diagram for the ZL2005P is illustrated in
Figure 5. In this circuit, the target output voltage is
regulated by connecting the VSEN pin directly to the
output regulat
ion point. The VSEN signal is then com-
pared to a reference voltage that has been set to the
de
sired output voltage level by the user. The error sig-
nal derived from this comparison is converted
to a dig-
ital value with a low-resolution analog t
o digital (A/D)
converter. The digital signal is applied to an adjustable
digital compensation filter, and the compensated sig-
nal is used to derive the appropriate PWM duty cyc
le
for driving the external MOSFETs in a way that pro-
duces the desired output.
The ZL2005P also incorporate
s a non-linear response
(NLR) loop to reduce the response time and output
deviation in response to a load transient. The ZL2005P
has an efficiency optimization circuit that continu-
ously monitors the power converter’s operating condi-
tions and adjusts the turn-on and turn-of
f timing of the
high-side and low-side MOSFETs to optimize the
overall efficiency of the power supply.
4.4 Power Management Overview
The ZL2005P incorporates a wide range of configu-
rable power management features that are simple to
implement with
no external components. Addition-
ally, the ZL2005P includes circuit protection features
that continuously
safeguard the load from damage due
to unexpected system faults. The ZL2005P can contin-
uously monitor input voltage, output voltage/current,
inte
rnal temperature, and the temperature of an exter-
nal thermal diode. A Power Goo
d output signal is pro-
vided to enable power-on reset functionality
for an
external processor.
All power management functions can be configured
using
either simple pin configuration techniques (Fig-
ure 8) or via the I
2
C/SMBus interface. Monitoring
parameters can be pre-configured to provide alerts for
specific conditions. See Application
Note AN2013 for
more details on SMBus monitoring.
4.5 Multi-mode Pins
In order to simplify circuit design, the ZL2005P incor-
porates patented multi-mode pins that allow the user
to
easily configure many aspects of the device without
requiring the user to program the IC. For the ZL2005P
only a few of the power management features can be
configured using these pins. The multi-mode pins can
respond to four different connections as shown in
Table 5. Any combination of connections is allowed
among the multi-mode pins. These pins
are sampled
when power is applied or by issuing a PMBus Restore
command (See Application Note AN2013).
Table 5. Multi-mode Pin Configuration
GND
(Logic low)
< 0.8 V
DC
OPEN
(N/C)
No connection
HIGH
(Log
ic high)
> 2.0 V
DC
Resistor to SGND Set by resistor value
Pin Tied To Value
ZL2005P
