Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

ZL2005PALRFT

Part # ZL2005PALRFT
Description IC REG CNTRLR BUCK PWM 36-QFN
Category IC
Availability In Stock
Qty 200
Qty Price
1 - 42 $4.32646
43 - 84 $3.44150
85 - 126 $3.24484
127 - 168 $3.01541
169 + $2.68765
Manufacturer Available Qty
Zilker Labs
Date Code: 1010
  • Shipping Freelance Stock: 100
    Ships Immediately
Zilker Labs
Date Code: 1010
  • Shipping Freelance Stock: 90
    Ships Immediately
Zilker Labs
  • Shipping Freelance Stock: 10
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

40
FN6849.3
December 16, 2011
FN6849.1 1. Electrical Chracteristics, Table 1:
a. Added “ISENA” to “Analog input voltages” with value of -3 to
6.5 and removed it’s stand-alone row with value of -1.5 to +30.
b. Removed 120mA row for “MOSFET drive reference”
and”Logic reference”.
2. Electrical Specifications, Table 3:
a. Changed “Logic input bias current” to ““Logic input leakage
current” with condition of “Push-pull logic” with Min of -250nA
and Max of 250nA.
b. Added Note 5 of “Limits established by charcterization and
not production tested” and callouts to the following parameters:
“Soft start delay duration range”, “Soft start ramp duration
range”, “Logic input leakage current”, “Minimum SYNC pulse
width”, “High-side driver peak gate drive current (pull down)”,
“High-side driver pull-up resistance”, “High-side driver pull-
down resistance”, “Low-side driver peak gate drive current (pull-
up)”, “Low-side driver peak gate drive current (pull-down)”,
“Low-side driver pull-up resistance
” , “Low-side driver pull-
down resistance
”, “Switching timing - GH and GL rise and fall”,
Power good delay range”, “VSEN undervoltage (and
overvolatge) threshold
” with condition of “Configurable via I2C/
SMBus
”, “VSEN undervoltage/overvoltage fault response
time
” with condition of “Configurable via I2C/SMBus”, “Current
limit protection delay
” with condition of “Configurable via I2C/
SMBus
”, “Thermal protection threshold” with condition of
Configurable via I2C/SMBus”.
3. Updated Ordering info to note R as the firmware revision
4. Updated Related documentation item numbers.
November 11, 2009
1. Updated Stamp on datasheet to read “Not Recommended
For New Designs Recommended Replacement Part
ZL6100
”.
November 12, 2009
FN6849.2 Page 5, Table 3, last row in the table "VTRK tracking threshold",
added a reference to Note 5.
August 12, 2010
Revision Number Description Date
ZL2005P
41
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6849.3
December 16, 2011
FN6849.3 Updated Caution statement in Table 1 on page 3 per legal's new
verbiage.
Updated Θ
JA
and Θ
JC
notes in Table 2 on page 4 to packaging's
standard notes.
Added standard over temp note to Min Max column of Table 3
on page 4 “Compliance to datasheet limits is assured by one or
more methods: production test, characterization and/or design."
Added standard "Boldface limits apply.." verbiage to common
conditions of
Table 3. Bolded applicable specs.
Corrected Figure 3 on page 9 to new POLA resistor value.
Corrected wording of “POLA/DOSA Trim Method” on page 15
to page 16.
Changed Table 8 on page 16 and Table 9 on page 16 to reflect
new POLA/DOSA values.
Replaced Zilker package outline drawing on page 38 with Intersil
equivalent (L36.6x6C). Changes as follows:
-Lead length in bottom view changed from 0.6±0.05 to 0.6±0.1
-Added land pattern
-Removed the following notes:
6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL
DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LASER MARKED.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE
EXPOSED HEAT SINK SLUG AS WELL AS THE
TERMINALS.
-Changed the JEDEC outline from MO-220 to MO-220VJJD.
Updated “Ordering Information” on page 39 from spider chart to
Intersil standard table, which includes lead finish note, MSL
note, tape and reel note and Intersil package outline drawing
number.
Updated sales disclaimer on last page to Intersil's verbiage
December 14, 2011
Revision Number Description Date
ZL2005P
PREVIOUS7891011121314