34
FN6849.3
December 16, 2011
6.9 I
2
C/SMBus Device Address Selection
When communicating with multiple ZL2005Ps using
the I
2
C/SMBus serial interface, each device must have
its own unique address so the host can distinguish
between the devices. The device address can be set
according to the pin-strap options listed in Table 27 to
provide up to eight unique device addresses. Address
values are
right-justified.
Table 27. Serial Bus Device Address Selection
If additional device addresses are required, a resistor
can be co
nnected to the SA0 pin according to Table 28
to provide up to 25 unique devic
e addresses. In this
case the SA1 pin should be tied to SGND with a zero
ohm resistor.
Table 28. SMBus Address Values
0x00 10 kΩ 0x0D 34.8 kΩ
0x01 11 kΩ 0x0E 38.3kΩ
0x02 12.1 kΩ 0x0F 42.2 kΩ
0x03 13.3 kΩ 0x10 46.4 kΩ
0x04 14.7 kΩ 0x11 51.1 kΩ
0x05 16.2 kΩ 0x12 56.2 kΩ
0x06 17.8 kΩ 0x13 61.9 kΩ
0x07 19.6 kΩ 0x14 68.1 kΩ
0x08 21.5 kΩ 0x15 75 kΩ
0x09 23.7 kΩ 0x16 82.5 kΩ
0x0A 26.1 kΩ 0x17 90.9 kΩ
0x0B 28.7 kΩ 0x18 100 kΩ
0x0C 31.6 kΩ
If more than 25 unique device addresses are required
or if
other SMBus address values are desired, both the
SA0 and SA1 pins can be configured with a resistor to
SGND according to the equation (30) and Table 29.
SMBus addr = 25x(SA1 index)+(SA0 index) (30)
Using this method, the user can theoretically configure
up to
625 unique SMBus addresses; however, the
SMBus is inherently limited to 128 devices so
attempting to configure an address higher than 128
will cause the device address to repeat (i.e, attempting
to configure a device address of 129 would result in a
device address of 1). Therefore, the user should use
index values 0-4 on the SA1 pin and the full range of
index values on the SA0 pin, which will provide 125
device address combinations.
Table 29. SMBus Address Index Values
0 10 kΩ 13 34.8 kΩ
1 11 kΩ 14 38.3 kΩ
2 12.1 kΩ 15 42.2 kΩ
3 13.3 kΩ 16 46.4 kΩ
4 14.7 kΩ 17 51.1 kΩ
5 16.2 kΩ 18 56.2 kΩ
6 17.8 kΩ 19 61.9 kΩ
7 19.6 kΩ 20 68.1 kΩ
8 21.5 kΩ 21 75 kΩ
9 23.7 kΩ 22 82.5 kΩ
10 26.1 kΩ 23 90.9 kΩ
11 28.7 kΩ 24 100 kΩ
12 31.6 kΩ
6.10 Phase Spreading
When multiple point of load converters share a com-
mon DC input supply, it is desira
ble to adjust the clock
phase offset of each device such that not all devices
start to switch simultaneously. Setting each converter
to start its switching cycle at a different point in time
can dramatically reduce input capacitance require-
ments and efficiency losses.
Since the peak current
drawn from the input supply is effectively spread out
over a period of time, the peak current drawn at any
given moment is reduced and the power losses propor-
tional to the I
RMS
2
are reduced dramatically.
In order to enable phase spreading,
all converters must
be synchronized to the same switching clock. The
CFG pin is used to set the configuration of the SYNC
pin for each device as described in Section 5.7,
“Switching Frequency and PLL,” .
SA1
LOW OPEN HIGH
SA0
LOW
0x20 0x23 0x26
OPEN
0x21 0x24 0x27
HIGH
0x22 0x25 Reserved
SMBus
Address
R
SA0
SMBus
Address
R
SA0
SA0 or
SA1 Index
R
SA
SA0 or
SA1
Index
R
SA
ZL2005P
