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SN74LVTH646PWR

Part # SN74LVTH646PWR
Description Bus XCVR Single 8-CH 3-ST 24-Pin TSSOP T/R - Tape and Reel
Category IC
Availability In Stock
Qty 1839
Qty Price
1 - 386 $0.61763
387 - 772 $0.49130
773 - 1,158 $0.46322
1,159 - 1,544 $0.43047
1,545 + $0.38368
Manufacturer Available Qty
Texas Instruments
Date Code: 0014
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
      
  
SCBS705H − AUGUST 1997 − REVISED MAY 2004
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
D I
off
and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH646 ...JT OR W PACKAGE
SN74LVTH646 . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
SN54LVTH646 . . . FK PACKAGE
(TOP VIEW)
5
6
7
8
9
10
11
25
24
23
22
21
20
19
432128
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
DIR
SAB
CLKAB
B8
B7
A8
GND
NC
NC
CLKBA
SBA
V
A7
B6
17 18
27 26
CC
NC − No internal connection
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
description/ordering information
These bus transceivers and registers are designed specifically for low-voltage (3.3-V) V
CC
operation, but with
the capability to provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE MARKING
SOIC − DW
Tube SN74LVTH646DW
LVTH646
SOIC − DW
Tape and reel SN74LVTH646DWR
LVTH646
SOP − NS Tape and reel SN74LVTH646NSR LVTH646
−40°C to 85°C
SSOP − DB Tape and reel SN74LVTH646DBR LXH646
−40 C to 85 C
TSSOP − PW
Tube SN74LVTH646PW
LXH646
TSSOP − PW
Tape and reel SN74LVTH646PWR
LXH646
TVSOP − DGV Tape and reel SN74LVTH646DGVR LXH646
CDIP − JT Tube SNJ54LVTH646JT SNJ54LVTH646JT
−55°C to 125°C
CFP − W Tube SNJ54LVTH646W SNJ54LVTH646W
−55 C to 125 C
LCCC − FK Tube SNJ54LVTH646FK SNJ54LVTH646FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 
      
  
SCBS705H − AUGUST 1997 − REVISED MAY 2004
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LVTH646 devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B
bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH646.
Output-enable (OE
) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
INPUTS
DATA I/Os
OPERATION OR FUNCTION
OE DIR CLKAB CLKBA SAB SBA A1−A8 B1−B8
OPERATION OR FUNCTION
X X X X X Input Unspecified
Store A, B unspecified
X XX X X Unspecified
Input Store B, A unspecified
H X X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
The data-output functions can be enabled or disabled by various signals at OE
and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
 
      
  
SCBS705H − AUGUST 1997 − REVISED MAY 2004
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
21
X
3
DIR
X
1
CLKAB
23
CLKBA
X
2
SAB
X
22
SBA
X
STORAGE FROM
A, B, OR A AND B
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
H
X
X
XX
X
X
X
L H H or L X H X
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OEOE
Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages.
Figure 1. Bus-Management Functions
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