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XC4VLX60-10FF1148I

Part # XC4VLX60-10FF1148I
Description FPGA VIRTEX-4 59904 CELLS 90NM 1.2V 1148FCBGA - Trays
Category IC
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Xilinx
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

DS112 (v3.1) August 30, 2010 www.xilinx.com
Product Specification 1
© Copyright 2004–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
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General Description
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4
family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC
technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and
combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the
PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a
state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.
Summary of Virtex-4 Family Features
Three Families — LX/SX/FX
- Virtex-4 LX: High-performance logic applications solution
- Virtex-4 SX: High-performance solution for digital signal
processing (DSP) applications
- Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
Xesium™ Clock Technology
- Digital clock manager (DCM) blocks
- Additional phase-matched clock dividers (PMCD)
- Differential global clocks
XtremeDSP™ Slice
- 18 x 18, two’s complement, signed Multiplier
- Optional pipeline stages
- Built-in Accumulator (48-bit) and Adder/Subtracter
Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically
remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
SelectIO™ Technology
- 1.5V to 3.3V I/O operation
- Built-in ChipSync™ source-synchronous technology
- Digitally controlled impedance (DCI) active termination
- Fine grained I/O banking (configuration in one bank)
Flexible Logic Resources
Secure Chip AES Bitstream Encryption
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging including Pb-Free Package
Choices
RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit
Transceiver (MGT) [FX only]
IBM PowerPC RISC Processor Core [FX only]
- PowerPC 405 (PPC405) Core
- Auxiliary Processor Unit Interface (User Coprocessor)
Multiple Tri-Mode Ethernet MACs [FX only]
0
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010
00
Product Specification
R
Table 1: Virtex-4 FPGA Family Members
Device
Configurable Logic Blocks (CLBs)
(1)
XtremeDSP
Slices
(2)
Block RAM
DCMs PMCDs
PowerPC
Processor
Blocks
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total
I/O
Banks
Max
User
I/O
Array
(3)
Row x Col
Logic
Cells Slices
Max
Distributed
RAM (Kb)
18 Kb
Blocks
Max
Block
RAM (Kb)
XC4VLX15 64 x 24 13,824 6,144 96
32
48 864 4 0 N/A N/A N/A 9 320
XC4VLX25 96 x 28 24,192 10,752 168
48
72 1,296 8 4 N/A N/A N/A 11 448
XC4VLX40 128 x 36 41,472 18,432 288
64
96 1,728 8 4 N/A N/A N/A 13 640
XC4VLX60 128 x 52 59,904 26,624 416
64
160 2,880 8 4 N/A N/A N/A 13 640
XC4VLX80 160 x 56 80,640 35,840 560
80
200 3,600 12 8 N/A N/A N/A 15 768
XC4VLX100 192 x 64 110,592 49,152 768
96
240 4,320 12 8 N/A N/A N/A 17 960
XC4VLX160 192 x 88 152,064 67,584 1056
96
288 5,184 12 8 N/A N/A N/A 17 960
XC4VLX200 192 x 116 200,448 89,088 1392
96
336 6,048 12 8 N/A N/A N/A 17 960
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010 www.xilinx.com
Product Specification 2
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System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
Up to twenty Digital Clock Manager (DCM) modules
- Precision clock deskew and phase shift
- Flexible frequency synthesis
- Dual operating modes to ease performance trade-off
decisions
- Improved maximum input/output frequency
- Improved phase shifting resolution
- Reduced output jitter
- Low-power operation
- Enhanced phase detectors
- Wide phase shift range
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Flexible Logic Resources
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
- Up to 178,176 internal registers with clock enable
(XC4VLX200)
- Up to 178,176 look-up tables (LUTs)
- Logic expanding multiplexers and I/O registers
Cascadable variable shift registers or distributed
memory capability
500 MHz XtremeDSP Slices
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
500 MHz Integrated Block Memory
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
- Full and Empty Flag support
- Fully programmable AF and AE Flags
- Synchronous/ Asynchronous Operation
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
XC4VSX25 64 x 40 23,040 10,240 160
128
128 2,304 4 0 N/A N/A N/A 9 320
XC4VSX35 96 x 40 34,560 15,360 240
192
192 3,456 8 4 N/A N/A N/A 11 448
XC4VSX55 128 x 48 55,296 24,576 384
512
320 5,760 8 4 N/A N/A N/A 13 640
XC4VFX12 64 x 24 12,312 5,472 86
32
36 648 4 0 1 2 N/A 9 320
XC4VFX20 64 x 36 19,224 8,544 134
32
68 1,224 4 0 1 2 8 9 320
XC4VFX40 96 x 52 41,904 18,624 291
48
144 2,592 8 4 2 4 12 11 448
XC4VFX60 128 x 52 56,880 25,280 395
128
232 4,176 12 8 2 4 16 13 576
XC4VFX100 160 x 68 94,896 42,176 659
160
376 6,768 12 8 2 4 20 15 768
XC4VFX140 192 x 84 142,128 63,168 987
192
552 9,936 20 8 2 4 24 17 896
Notes:
1. One CLB = Four Slices = Maximum of 64 bits.
2. Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
3. Some of the row/column array is used by the processors in the FX devices.
Table 1: Virtex-4 FPGA Family Members (Continued)
Device
Configurable Logic Blocks (CLBs)
(1)
XtremeDSP
Slices
(2)
Block RAM
DCMs PMCDs
PowerPC
Processor
Blocks
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total
I/O
Banks
Max
User
I/O
Array
(3)
Row x Col
Logic
Cells Slices
Max
Distributed
RAM (Kb)
18 Kb
Blocks
Max
Block
RAM (Kb)
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010 www.xilinx.com
Product Specification 3
R
SelectIO Technology
Up to 960 user I/Os
Wide selections of I/O standards from 1.5V to 3.3V
Extremely high-performance
- 600 Mb/s HSTL & SSTL (on all single-ended I/O)
- 1 Gb/s LVDS (on all differential I/O pairs)
True differential termination
Selected low-capacitance I/Os for improved signal
integrity
Same edge capture at input and output I/Os
Memory interface support for DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
ChipSync Technology
Integrated with SelectIO technology to simplify
source-synchronous interfaces
Per-bit deskew capability built in all I/O blocks (variable
input delay line)
Dedicated I/O and regional clocking resources (pin and
trees)
Built in data serializer/deserializer logic in all I/O and
clock dividers
Memory/Networking/Telecommunication interfaces up
to 1 Gb/s+ DDR
Digitally Controlled Impedance (DCI)
Active I/O Termination
Optional series or parallel termination
Temperature compensation
Configuration
256-bit AES bitstream decryption provides intellectual
property (IP) security
Improved bitstream error detection/correction capability
Fast SelectMAP configuration
JTAG support
Readback capability
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging
Pb-Free packages available with production devices.
System Blocks Specific to the Virtex-4 FX Family
RocketIO Multi-Gigabit Transceiver (MGT)
Full-duplex serial transceiver (MGT) capable of
622 Mb/s to 6.5 Gb/s baud rates
8B/10B, 64B/66B, user-defined FPGA logic, or no data
encoding/decoding
Channel bonding support
CRC generation and checking
Programmable TX pre-emphasis or pre-equalization
Programmable RX continuous time equalization
Programmable RX decision feedback equalization
On-chip RX AC coupling
RX signal detect and loss of signal indicator
TX driver electrical idle mode
User dynamic reconfiguration using secondary
configuration bus
PowerPC 405 Processor RISC Core
Embedded PowerPC 405 processor (PPC405) core
- Up to 450 MHz operation
- Five-stage data path pipeline
- 16 KB instruction cache
- 16 KB data cache
- Enhanced instruction and data on-chip memory
(OCM) controllers
- Additional frequency ratio options between
PPC405 and Processor Local Bus
Auxiliary Processor Unit (APU) Interface for direct
connection from PPC405 to coprocessors in fabric
- APU can run at different clock rates
- Supports autonomous instructions: no pipeline stalls
- 32-bit instruction and 64-bit data
- 4-cycle cache line transfer
Tri-Mode Ethernet Media Access Controller
IEEE 802.3 compliant
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-detect
Receive address filter
Fully monolithic 1000Base-X solution with RocketIO
MGT
Implements SGMII through RocketIO MGT to external
PHY device
Supports multiple PHY (MII, GMII, etc.) interfaces
through an I/O resource
Receive and transmit statistics available through
separate interfaces
Separate host and client interfaces
Support for jumbo frames
Flexible, user-configurable host interface
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