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XC4VFX100-11FF1152I

Part # XC4VFX100-11FF1152I
Description FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1152FCBGA - Trays
Category IC
Availability In Stock
Qty 2
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1 + $5,300.33071
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Xilinx
Date Code: 1105
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 28
Input Serializer/Deserializer Switching Characteristics
Tabl e 34 : ISERDES Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
Setup/Hold for Control Lines
T
ISCCK_BITSLIP
/ T
ISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
0.28
–0.20
0.34
–0.16
0.40
–0.13
ns
T
ISCCK_CE
/ T
ISCKC_CE
(2)
CE pin Setup/Hold with respect to CLK (for CE1)
0.48
–0.37
0.57
–0.30
0.69
–0.25
ns
T
ISCCK_CE2
/ T
ISCKC_CE2
(2)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
0.11
–0.04
0.14
–0.03
0.16
–0.02
ns
T
ISCCK_DLYCE
/ T
ISCKC_DLYCE
DLYCE pin Setup/Hold with respect to CLKDIV
0.16
0.11
0.19
0.13
0.23
0.16
ns
T
ISCCK_DLYINC
/ T
ISCKC_DLYINC
DLYINC pin Setup/Hold with respect to CLKDIV
0.01
0.36
0.01
0.43
0.01
0.51
ns
T
ISCCK_DLYRST
/ T
ISCKC_DLYRST
DLYRST pin Setup/Hold with respect to CLKDIV
–0.03
0.37
–0.02
0.45
–0.02
0.54
ns
T
ISCCK_SR
SR pin Setup with respect to CLKDIV 0.64 0.77 0.92 ns
Setup/Hold for Data Lines
T
ISDCK_D
/ T
ISCKD_D
D pin Setup/Hold with respect to CLK
(IOBDELAY = IBUF or NONE)
0.24
–0.11
0.28
–0.11
0.34
–0.11
ns
D pin Setup/Hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
6.64
–6.51
7.63
–6.51
8.84
–6.51
ns
D pin Setup/Hold with respect to CLK
(1)
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.81
–0.68
0.87
–0.68
1.08
–0.68
ns
T
ISDCK_DDR
/ T
ISCKD_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE)
0.24
–0.11
0.28
–0.11
0.34
–0.11
ns
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
6.64
–6.51
7.63
–6.51
8.84
–6.51
ns
D pin Setup/Hold with respect to CLK at DDR mode
(1)
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.81
–0.68
0.87
–0.68
1.08
–0.68
ns
Sequential Delays
T
ISCKO_Q
CLKDIV to out at Q pin 0.59 0.71 0.85 ns
Propagation Delays
T
ISDO_DO_IOBDELAY_IFD
D input to DO output pin (IOBDELAY = IFD) 0.17 0.20 0.24 ns
T
ISDO_DO_IOBDELAY_NONE
D input to DO output pin (IOBDELAY = NONE) 0.17 0.20 0.24 ns
T
ISDO_DO_IOBDELAY_BOTH
D input to DO output pin
(IOBDELAY = BOTH,
IOBDELAY_TYPE = DEFAULT)
6.00 6.91 7.96 ns
D input to DO output pin
(1)
(IOBDELAY = BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.74 0.79 0.99 ns
T
ISDO_DO_IOBDELAY_IBUF
D input to DO output pin
(IOBDELAY = IBUF,
IOBDELAY_TYPE = DEFAULT)
6.00 6.91 7.96 ns
D input to DO output pin
(1)
(IOBDELAY = IBUF,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.74 0.79 0.99 ns
Notes:
1. Recorded at 0 tap value. Refer to Timing Report for other values.
2. T
ISCCK_CE2
and T
ISCKC_CE2
are reported as T
ISCCK_CE
/ T
ISCKC_CE
in TRCE report.
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 29
Input Delay Switching Characteristics
Tabl e 35 : Input Delay Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
IDELAYCTRL
T
IDELAYCTRLCO_RDY
Reset to Ready for IDELAYCTRL
(Maximum)
3.00 3.00 3.00 µs
F
IDELAYCTRL_REF
REFCLK frequency 200 200 200
MHz
IDELAYCTRL_REF_PRECISION
(2)
REFCLK precision ±10 ±10 ±10
MHz
T
IDELAYCTRL_RPW
Minimum Reset pulse width 50.0 50.0 50.0 ns
IDELAY
T
IDELAYRESOLUTION
IDELAY Chain Delay Resolution 75 75 75 ps
T
IDELAYTOTAL_ERR
Cumulative delay at a given tap
(3)
[(tap −1) x 75 +34]
± 0.07[(tap −1) x 75 +34]
ps
T
IDELAYPAT_JIT
Pattern dependent period jitter in delay
chain for clock pattern
000
Note (4)
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
10 ± 2 10 ± 2 10 ± 2
Note (4)
F
MAX
C clock maximum frequency 300 250 250
MHz
Notes:
1. Refer to Xilinx Application Note XAPP707 for details on IDELAY timing characteristics.
2. See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, SelectIO Logic Resources.
3. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
4. Units in ps peak-to-peak per tap.
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 30
Output Serializer/Deserializer Switching Characteristics
Tabl e 36 : OSERDES Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
Setup/Hold
T
OSDCK_D
/ T
OSCKD_D
D input Setup/Hold with respect to CLKDIV
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
T
OSDCK_T
/ T
OSCKD_T
(1)
T input Setup/Hold with respect to CLK
0.43
–0.16
0.52
–0.16
0.62
–0.16
ns
T
OSDCK_T2
/ T
OSCKD_T2
(1)
T input Setup/Hold with respect to CLKDIV
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
T
OSCCK_OCE
/ T
OSCKC_OCE
OCE input Setup/Hold with respect to CLK
0.45
0.01
0.53
0.02
0.64
0.03
ns
T
OSCCK_S
SR (Reset) input Setup with respect to CLKDIV 0.67 0.80 0.96 ns
T
OSCCK_TCE
/ T
OSCKC_TCE
TCE input Setup/Hold with respect to CLK
0.45
0.01
0.53
0.02
0.64
0.03
ns
Sequential Delays
T
OSCKO_OQ
Clock to out from CLK to OQ 0.41 0.49 0.59 ns
T
OSCKO_TQ
Clock to out from CLK to TQ 0.41 0.49 0.59 ns
Combinatorial
T
OSDO_TTQ
T input to TQ Out 0.56 0.65 0.76 ns
T
OSCO_OQ
Asynchronous Reset to OQ 1.14 1.37 1.64 ns
T
OSCO_TQ
Asynchronous Reset to TQ 1.14 1.37 1.64 ns
Notes:
1. T
OSDCK_T2
and T
OSCKD_T2
are reported as T
OSDCK_T
/ T
OSCKD_T
in TRCE report.
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