Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 25
HSTL, Class IV, 1.8V HSTL_IV_18 25 0 1.1 1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 V
REF
0.9
SSTL, Class II, 1.8V SSTL18_II 25 0 V
REF
0.9
SSTL, Class I, 2.5V SSTL2_I 50 0 V
REF
1.25
SSTL, Class II, 2.5V SSTL2_II 25 0 V
REF
1.25
LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 50 0 V
REF
1.2
LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 50 0 V
REF
1.2
BLVDS (Bus LVDS), 2.5V BLVDS_25 1M 0 1.2 0
LDT (HyperTransport), 2.5V LDT_25 50 0 V
REF
0.6
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25 1M 0 0.90 0
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33, HSLVDCI_33 1M 0 1.65 0
LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_25 1M 0 1.25 0
LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_18 1M 0 0.9 0
LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 1M 0 0.75 0
HSTL (High-Speed Transceiver Logic), Class I & II, with
DCI
HSTL_I_DCI, HSTL_II_DCI 50 0 V
REF
0.75
HSTL, Class III & IV, with DCI HSTL_III_DCI, HSTL_IV_DCI 50 0 0.9 1.5
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18,
HSTL_II_DCI_18
50 0 V
REF
0.9
HSTL, Class III & IV, 1.8V, with DCI
HSTL_III_DCI_18,
HSTL_IV_DCI_18
50 0 1.1 1.8
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 50 0 V
REF
0.9
SSTL, Class I & II, 2.5V, with DCI SSTL2_I_DCI, SSTL2_II_DCI 50 0 V
REF
1.25
GTL (Gunning Transceiver Logic) with DCI GTL_DCI 50 0 0.8 1.2
GTL Plus with DCI GTLP_DCI 50 0 1.0 1.5
Notes:
1. C
REF
is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. Per PCI-X specifications.
Tabl e 31 : Output Delay Measurement Methodology (Continued)
Description
I/O Standard
Attribute
R
REF
(Ω)
C
REF
(1)
(pF)
V
MEAS
(V)
V
REF
(V)
