Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 24
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4 inches
of FR4 microstrip trace. Standard termination was used for
all testing. The propagation delay of the 4 inch trace is char-
acterized separately and subtracted from the final measure-
ment, and is therefore not included in the generalized test
setup shown in Figure 4.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. Parame-
ters V
REF
, R
REF
, C
REF
, and V
MEAS
fully describe the test
conditions for each I/O standard. The most accurate predic-
tion of propagation delay in any given application can be
obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Ta bl e 3 1.
2. Record the time to V
MEAS
.
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V
MEAS
.
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual worst-case
propagation delay (clock-to-input) of the PCB trace.
Figure 4: Generalized Test Setup
V
REF
R
REF
V
MEAS
(voltage level when taking
delay measurement)
C
REF
(probe capacitance)
FPGA Output
DS302_05_031708
Tabl e 31 : Output Delay Measurement Methodology
Description
I/O Standard
Attribute
R
REF
(Ω)
C
REF
(1)
(pF)
V
MEAS
(V)
V
REF
(V)
LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL (all) 1M 0 1.4 0
LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 1M 0 1.65 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0
LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0
LVCMOS, 1.2V LVCMOS12 1M 0 0.75 0
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI33_3 (rising edge) 25 10
(2)
0.94 0
PCI33_3 (falling edge) 25 10
(2)
2.03 3.3
PCI, 66 MHz, 3.3V
PCI66_3 (rising edge) 25 10
(2)
0.94 0
PCI66_3 (falling edge) 25 10
(2)
2.03 3.3
PCI-X, 133 MHz, 3.3V
PCIX (rising edge) 25 10
(3)
0.94
PCIX (falling edge 25 10
(3)
2.03 3.3
GTL (Gunning Transceiver Logic) GTL 25 0 0.8 1.2
GTL Plus GTLP 25 0 1.0 1.5
HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 V
REF
0.75
HSTL, Class II HSTL_II 25 0 V
REF
0.75
HSTL, Class III HSTL_III 50 0 0.9 1.5
HSTL, Class IV HSTL_IV 25 0 0.9 1.5
HSTL, Class I, 1.8V HSTL_I_18 50 0 V
REF
0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 V
REF
0.9
HSTL, Class III, 1.8V HSTL_III_18
50 0 1.1 1.8
