Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 16

RocketIO Switching Characteristics

Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further information.

Tabl e 22 : Processor Block APU Interface Switching Characteristics

Description Symbol

Speed Grade

Units-12 -11 -10

Setup and Hold Relative to Clock (CPMDFCMCLOCK)

APU bus control inputs

PPCDCK

_DCDCREN

PPCCKD

_DCDCREN

0.33

0.20

0.36

0.20

0.42

0.23

ns, Min

APU bus data inputs

PPCDCK

_RESULT

PPCCKD

_RESULT

0.61

0.20

0.67

0.20

0.78

0.23

ns, Min

Clock to Out

APU bus control outputs T

PPCCKO

_APUFCMDEC 1.53 1.75 2.00 ns, Max

APU bus data outputs T

PPCCKO

_RADATA 1.53 1.75 2.00 ns, Max

Tabl e 23 : Maximum RocketIO Transceiver Performance

Description

Speed Grade

Units-12 -11 -10

RocketIO Transceiver 6.5 6.5 3.125 Gb/s

Tabl e 24 : RocketIO Reference Clock Switching Characteristics

Description Symbol Conditions Min Typ Max Units

Reference Clock frequency range

(1)

GCLK

CLK

-10 Speed Grade

106 400 MHz

-11/-12 Speed Grades

106 644 MHz

All Speed Grades

GREFCLK Reference Clock frequency range

(1)

GREFCLK

CLK 106 320 MHz

Reference Clock frequency tolerance F

GTOL

CLK –350 +350 ppm

Reference Clock rise time T

RCLK

20% – 80% 400 ps

Reference Clock fall time T

FCLK

20% – 80% 400 ps

Reference Clock duty cycle T

DCREF

CLK 45 55 %

Reference Clock total jitter, peak-peak

(2)

GJTT

CLK 40 ps

Clock recovery frequency acquisition time T

LOCK

Initial lock of the PLL from

startup (programmable)

1ms

Spread Spectrum Clocking

(3)

0% to –0.5% 30 33 kHz

Notes:

1. MGTCLK input can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s.

2. Measured at the package pin. For serial rates equal to or above 1 Gb/s, MGTCLK must be used. UI = Unit Interval.

3. Tested with synchronous reference clock.

Figure 3: Reference Clock Timing Parameters

DS302_04_031708

80%

20%

FCLK

RCLK

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 17

Tabl e 25 : RocketIO Receiver Switching Characteristics

Description Symbol Conditions Min Typ Max Units

Serial data rate, -10 F

GRX

0.622 3.125 Gb/s

Serial data rate, -11 F

GRX

0.622 6.5 Gb/s

XAUI Receive Jitter Tolerance (8B/10B CJPAT)

(2)

Rate (Gb/s) Mode

(3)

Frequency

Receive Deterministic Jitter Tolerance T

DJTOL

3.125 ACDR 0.37

(1)

Receive Total Jitter Tolerance T

TJTOL

(6)

3.125 ACDR 0.65

Receive Sinusoidal Jitter Tolerance T

SJTOL

(7)

3.125 ACDR f = 22.1 kHz 8.5

3.125 ACDR f = 1.875 MHz 0.10

3.125 ACDR f = 20 MHz 0.10

General Receive Jitter Tolerance Rate (Gb/s) Mode

(3)

Pattern

Receive deterministic jitter tolerance T

DJTOL

(2,4)

6.5

(5)

ACDR PRBS7 0.65

(1)

5.0

(5)

ACDR PRBS7 0.65

4.25

(5)

ACDR PRBS7 0.65

3.125 ACDR PRBS7 0.60

2.5 ACDR PRBS7 0.55

1.25 ACDR PRBS7 0.50

1.25 DCDR PRBS7 0.50

1.25 DCDR PRBS31 0.40

0.622 DCDR PRBS31 0.40

Sinusoidal jitter tolerance T

SJTOL

6.5

(9)

ACDR PRBS7 0.65

5.0

(9)

ACDR PRBS7 0.65

4.25

(9)

ACDR PRBS7 0.65

3.125

(8)

ACDR PRBS7 0.50

2.5

(8)

ACDR PRBS7 0.50

1.25

(8)

ACDR PRBS7 0.50

1.25

(8)

DCDR PRBS7 0.55

1.25

(8)

DCDR PRBS31 0.35

0.622

(8)

DCDR PRBS31 0.55

RXUSRCLK frequency T

For slower speed grades = MaxDataRate/32 250 MHz

RXUSRCLK2 frequency T

RX2

250 MHz

RXUSRCLK duty cycle T

RXDC

40 60 %

RXUSRCLK2 duty cycle T

RX2DC

40 60 %

Differential input skew T

ISKEW

20 ps

Differential receive input sensitivity

(2)

EYE

110 mV

On-chip AC coupling corner frequency

Signal detect response time RXSIGDET

Responsetime

30 ns

Input capacitance at the Die C

DIE

Excess capacitance at the solder ball C

BALL

Notes:

1. UI = Unit Interval

2. Using receiver equalization setting of 111 (14 dB).

3. ACDR = Analog CDR and DCDR = Digital CDR.

4. Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency

sinusoidal jitter (SJ).

5. Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ +

0.15 UI of RJ.

6. Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter

as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5.

7. SJ in addition to 0.55 UI of DJ +RJ.

8. Jitter frequency = 5 MHz.

9. Jitter frequency = 10 MHz.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 18

Tabl e 26 : RocketIO Transmitter Switching Characteristics

Description Symbol Conditions

Min Typ Max Units

Serial data rate, -10 F

GTX

0.622 3.125 Gb/s

Serial data rate, -11 F

GTX

0.622 6.5 Gb/s

Data Rate (Gb/s)

TX Jitter Generation

(3)

PRBS7 6.5

0.50

(1)

0.35

0.30

PRBS7 5.0

0.45

0.30

0.25

PRBS7 4.25

0.40

0.25

0.21

PRBS7 3.125

0.28

0.14

PRBS7 2.5

0.25

0.18

0.12

PRBS7 1.25

0.12

0.10

0.06

PRBS31 0.622

0.08

0.06

0.04

TX rise time

(2)

RTX

20% – 80% 90 ps

TX fall time

(2)

FTX

20% – 80% 90 ps

TXUSRCLK frequency

For slower speed grades =

MaxDataRate/32

250 MHz

TXUSRCLK2 frequency 250 MHz

TXUSRCLK duty cycle T

TXDC

40 60 %

TXUSRCLK2 duty cycle T

TX2DC

40 60 %

Differential output skew T

ISKEW

12 20 ps

Electrical idle transition time TXOOB

Tra nsit ion

15 ns

Notes:

1. UI = Unit Interval.

2. Default attributes, measured at 2.5 Gb/s.

3. Peak-to-Peak values measured relative to 1e-12 Error rate. Default attributes. TX feedback divider (TXPLLNDIVSEL) = 10.

Part #	XC4VFX100-11FF1152I
Description	FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1152FCBGA - Trays
Category	IC
Availability	In Stock
Qty	2

XC4VFX100-11FF1152I

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