Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 15
Tabl e 19 : PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Description Symbol
Speed Grade
Units-12 -11 -10
Setup and Hold Relative to Clock (BRAMDSOCMCLK)
Data-Side On-Chip Memory data bus inputs
T
PPCDCK
_DSOCMRDDB
T
PPCCKD
_DSOCMRDDB
0.60
0.20
0.65
0.20
0.74
0.23
ns, Min
Clock to Out
Data-Side On-Chip Memory control outputs T
PPCCKO
_BRAMBWR 2.07 2.30 2.65 ns, Max
Data-Side On-Chip Memory address bus outputs T
PPCCKO
_BRAMABUS 2.07 2.30 2.65 ns, Max
Data-Side On-Chip Memory data bus outputs T
PPCCKO
_IBRAMWRDBUS01 1.61 1.79 2.06 ns, Max
Tabl e 20 : PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
Description Symbol
Speed Grade
Units-12 -11 -10
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Instruction-Side On-Chip Memory data bus inputs
T
PPCDCK
_ISOCMRDDB
T
PPCCKD
_ISOCMRDDB
0.74
0.20
0.82
0.20
0.94
0.23
ns, Min
Clock to Out
Instruction-Side On-Chip Memory control outputs T
PPCCKO
_IBRAMEN 3.04 3.37 3.88 ns, Max
Instruction-Side On-Chip Memory address bus outputs T
PPCCKO
_IBRAMRDABUS 1.67 1.85 2.13 ns, Max
Instruction-Side On-Chip Memory data bus outputs T
PPCCKO
_IBRAMWRDBUS 1.67 1.86 2.14 ns, Max
Tabl e 21 : Processor Block DCR Bus Switching Characteristics
Description Symbol
Speed Grade
Units-12 -11 -10
Setup and Hold Relative to Clock (CPMDCRCLOCK)
Device Control Register Bus control inputs
T
PPCDCK
_EXDCRACK
T
PPCCKD
_EXDCRACK
0.12
0.15
0.13
0.17
0.15
0.19
ns, Min
Device Control Register Bus data inputs
T
PPCDCK
_EXDCRDBUSI
T
PPCCKD
_EXDCRDBUSI
0.57
0.16
0.57
0.16
1.02
0.27
ns, Min
Clock to Out
Device Control Register Bus control outputs T
PPCCKO
_EXDCRRD 1.20 1.35 1.54 ns, Max
Device Control Register Bus address bus outputs T
PPCCKO
_EXDCRABUS 1.28 1.45 1.66 ns, Max
Device Control Register Bus data bus outputs T
PPCCKO
_EXDCRDBUSO 1.31 1.45 1.67 ns, Max
