Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 12
Interface Performance Characteristics
Switching Characteristics
Switching characteristics are specified on a per-speed-
grade basis and can be designated as Advance, Prelimi-
nary, or Production. Each designation is defined as follows:
Advance
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some
under-reporting might still occur.
Preliminary
These specifications are based on complete ES (engineer-
ing sample) silicon characterization. Devices and speed
grades with this designation are intended to give a better
indication of the expected performance of production sili-
con. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production
These specifications are released once enough production
silicon of a particular device family member has been char-
acterized to provide full correlation between specifications
and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal
notification of any subsequent changes. Typically, the slow-
est speed grades transition to Production before faster
speed grades.
Tabl e 1 4 correlates the current status of each Virtex-4
device with a corresponding speed specification version
1.68 designation.
Tabl e 13 : Interface Performance
Description
Speed Grade
-12 -11 -10
Networking Applications
SFI-4.1 (SDR LVDS Interface)
(1)
710 MHz 710 MHz 645 MHz
SPI-4.2 (DDR LVDS Interface) 1 Gb/s 1 Gb/s 800 Mb/s
Memory Interfaces
DDR2 SDRAM (High-Performance SERDES Design)
(2)
600 Mb/s 533 Mb/s 500 Mb/s
DDR2 SDRAM (Low-Latency Direct Clocking Design)
(3)
420 Mb/s 410 Mb/s 400 Mb/s
QDRII SRAM (Low-Latency Direct Clocking Design)
(4)
550 Mb/s 500 Mb/s 400 Mb/s
DDR SDRAM (Low-Latency Direct Clocking Design)
(5)
344 Mb/s 336 Mb/s 330 Mb/s
RLDRAM II (Low-Latency Direct Clocking Design)
(6)
470 Mb/s 470 Mb/s 400 Mb/s
Notes:
1. Input clocks above 622 MHz require AC coupling.
2. Performance defined using design implementation described in application note XAPP721
, High-Performance DDR2 SDRAM Interface Data
Capture Using ISERDES and OSERDES.
3. Performance defined using design implementation described in application note XAPP702
, DDR2 Controller Using Virtex-4 Devices.
4. Performance defined using design implementation described in application note XAPP703
, QDR II SRAM Interface for Virtex-4 Devices.
5. Performance defined using design implementation described in application note XAPP709
, DDR SDRAM Controller Using Virtex-4 FPGA Devices.
6. Performance defined using design implementation described in application note XAPP710
, Synthesizable CIO DDR RLDRAM II Controller for
Virtex-4 FPGAs.
Table 14: Virtex-4 Device Speed Grade Designations
Device
Speed Grade Designations
Advance Preliminary Production
XC4VLX15 -12, -11, -10
XC4VLX25 -12, -11, -10
XC4VLX40 -12, -11, -10
XC4VLX60 -12, -11, -10
XC4VLX80 -12, -11, -10
XC4VLX100 -12, -11, -10
XC4VLX160 -12, -11, -10
XC4VLX200 -11, -10
XC4VSX25 -12, -11, -10
XC4VSX35 -12, -11, -10
XC4VSX55 -12, -11, -10
XC4VFX12 -12, -11, -10
XC4VFX20 -12, -11, -10
XC4VFX40 -12, -11, -10
XC4VFX60 -12, -11, -10
XC4VFX100 -12, -11, -10
XC4VFX140 -11, -10
