Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 55
09/07/06 1.16 Added 2.5V rows to V
IN
and V
TS
(Table 1, page 1). Updated value DV
IN
from 200 mV to
110 mV in Table 12, page 11. Updated speed grade specifications for XCV4FX devices in
Tabl e 1 4 . Updated jitter tolerance and V
EYE
in Table 25, page 17. Corrected equation for
T
IDELAYTOTAL_ERR
in Table 35, page 29.
10/06/06 1.17
• SPEED SPECIFICATION version for this data sheet release: v1.62.
• Table 1 : Removed former note 3 on V
IN
.
• Table 1 4 : Moved XC4VFX12-11, XC4VFX20-11, XC4VFX60-11, and XC4VFX100-11
devices to Production status.
• Table 1 5 : Expanded to break out processor clock specifications into Characteristics
when APU Not Used and Characteristics when APU Used. Removed specs for
CPMFCMCLK, not available.
• Table 2 5 , Tabl e 2 6: Updated RX and TX jitter data and notes.
• Table 3 9 : Modified T
REGXB
, T
REGYB
, and T
CKSH
timing parameters to comply with
v1.62 speed specification.
12/11/06 2.0
• SPEED SPECIFICATION version for this data sheet release: v1.62.
• Table 1 : Modified Note (3) referring to 3.3V I/O design guidelines. Added I
IN
parameters.
• Table 2 : Corrected recommended V
TRX
range to 0.25V – 2.5V. Added I
IN
parameters.
• Table 7 : Added LVDCI attributes with LVCMOS.
• Table 1 3 : Added Note (1) for SDR LVDS Interface requiring AC coupling above
622 MHz. Added DDR2 SDRAM (High-Performance SERDES Design) with reference
to XAPP721. Updated all specification values.
• Pin-to-Pin Performance and Register-to-Register Performance tables (formerly Table
13 and Table 14) deleted.
• Table 1 4 : XC4VFX12 changed to Production status.
• Table 1 5 : Added APU-used max characteristics for -12 devices.
• Table 2 4 : Added values for Spread-Spectrum Clocking and footnote.
• Table 2 6 : Changed symbol for jitter parameters from T
J
, R
J
, and D
J
to TJ, RJ, and DJ
respectively.
• Table 3 2 : Added Note (1) to refer to Timing Report for non-zero tap values. Made DLY
setup/hold parameters relative to C, not CLKDIV.
• Table 3 4 : Amended Note (1) to refer to Timing Report for non-zero tap values.
• Table 3 5 : Added Note (1) to refer to XAPP707 for details on IDELAY timing
characteristics. Changed T
IDELAYRESOLUTION
from 74 ps to 75 ps to match Timing
Analyzer. Modified formula for T
IDELAYTOTAL_ERR
to use 75 ps resolution.
• Table 4 0 : Added CLK-to-DOUT parameters for “with ECC” case. Added CLK-to-CLK
parameter.
• Table 4 3 , Tabl e 4 4, Tabl e 59 : Added configuration parameter values for -12 speed
grade.
• Table 4 5 : Added F
MAX
for -12 speed grade.
• Table 4 5 , Tabl e 4 6, Tabl e 47 : Added Note (6) stating that CLKIN values for DLL only
also apply to DLL and DFS together.
• Table 4 6 , Tabl e 4 7: Replicated Note (5) from Tabl e 4 5 and applied to all CLKIN with
DLL parameters.
• Table 4 7 , Tabl e 5 0: Added notes to clarify boundary-frequency cases.
• Table 4 8 : Modified Note (1) to point to the architecture wizard for CLKFX output jitter.
Added Note (2) to indicate that PMCD outputs introduce no jitter.
Date Version Revisions
