Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 54
02/03/06 1.11 Revised the speed specification requirements in Switching Characteristics, page 12, with
parameter changes in Tab l e 54 and Ta ble 5 6. Added Note 7 to Ta ble 2 . Added to the I
RPU
and I
RPD
specifications in Ta bl e 3. Changed LVCMOS18 to meet the JEDEC specification in
Tabl e 7 . Inserted notes into Ta ble 8, Ta bl e 9 , and Ta bl e 10. Corrected note 1 in Tabl e 1 1 . In
Tabl e 1 2 , revised Common Mode Input Voltage Range (V
ICM
) typical from 800 mV to
600 mV and added a new Note 1. Also in Ta bl e 1 2, changed Common Mode Voltage
specification from 95mV to 950mV. Changed performance numbers in Tabl e 2 3 . Removed
the typical specification for T
DJ
from Tabl e 2 6 . Added note 2 to Ta ble 27. In Ta ble 3 5, added
maximum to
T
IDELAYCTRLCO_RDY
, and a new parameter T
IDELAYPAT_JIT
. Revised Note 1 in
Tabl e 4 3 . Added note 5 to Tabl e 4 5 . Revised notes 3 and 5 in Tab l e 50. Changed the
CLKIN_FREQ_PMCD_CLKA_MAX -12 specification in Ta ble 5 3 . Changed the
T
BUFIO_MAX_FREQ
specification in Ta bl e 5 9 . Changed the information in the Production
Stepping and Current Virtex-4 Production Devices sections.
03/22/06 1.12 Modified second paragraph in Power-On Power Supply Requirements. Added/Changed
numbers for I
CCINTMIN
, I
CCAUXMIN
, and I
CCOMIN,
and added Note 2 (Tab l e 5). Changed the
typ value of the DC Parameter, Common Mode Input Voltage Range from 600 MV to
800 MV in Ta b le 12. Added three DC parameters to Tabl e 12 , Input Common-Mode Voltage
(V
ICMC
), Peak-to-Peak Differential Input Voltage (V
IDIFF
), and Differential Input Resistance
(R
IN
). Changed the SPI4.2 entry for -11 from 900 Mb/s to 1 Gb/s in Ta bl e 1 3. Added Note 3
to Tabl e 15 . Reduced the maximum frequency from 322 MHz to 250 MHz (in Tabl e 2 5 and
Tabl e 2 6 ). Added Note 5 to Tabl e 40 .
06/01/06 1.13 Changed
V
IN
and V
TS
values and added notes to Table 1, page 1. Removed -11X speed
grade from Ta ble 1 4 . Updated to speed specification v1.60. Removed -11X speed grade,
changed the -12 and -11 speed grade to 6.5 Gb/s, and deleted Note 1 in Table 23, page 16.
Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Reference
Clock total jitter, peak-peak (T
GJTT
) in Table 24, page 16. Changed the max value for Serial
data rate F
GTX
to 6.5 Gb/s. Deleted first condition and changed second condition to
2.5 Gb/s to 6.5 Gb/s for Serial data output deterministic jitter (T
DJ
) and deleted first
condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output
random jitter (T
RJ
), both in Table 26, page 18.
06/23/06 1.14.1 Virtex-4 FPGA Electrical Characteristics, page 1: removed paragraph on that introduced
the -11x for XC4VFX devices. Table 3, page 3: added new values for I
CCAUXRX
, I
CCAUXTX
,
I
CCCAUXMGT
, I
TTX
, I
TRX
, and new notes 2 and 3. Table 4, page 4: added new symbols and
for values I
CCAUXRX
, I
CCAUXTX
, I
TTX
, I
TRX
,I
AUMGT
and new notes 4 and 5. Tabl e 12 ,
page 11: changed DC parameters and values and added note. Tabl e 14: changed speed
designations for the XC4VFX devices. Table 24, page 16 and Table 25, page 17, for most
characteristics: changed conditions, speed grade (typ and max) values, and units. Tabl e 2 6 ,
page 18, for most characteristics: changed conditions, speed grade (typ and max) values,
and units. Updated notes. Table 43, page 36: removed the Tcnfig symbol, values, and note
1. Note 2 is now Note 1, and the reference has also been changed. Table 50, page 42:
removed Input Signal Requirements. Table 54, page 44, Table 55, page 45, Ta bl e 5 6 ,
page 46, Table 57, page 47, and Table 58, page 48: corrected large speed numbers to N/A.
08/23/06 1.15 Table 24, page 16: changed value for Reference Clock Rise/Fall Time (T
RCLK
; T
FCLK
) from
65 ps Typ to 400 ps Max. Table 35, page 29: changed the speeds specification for the -12,
-11, and -10 Speed Grades for T
IDELAYRESOLUTION
, deleted row for
T
IDELAYRESOLUTION_ERR
and added row for T
IDELAYTOTAL_ERR
. Table 39, page 32: changed
the speeds specification for -12 Speed Grades, Sequential Delay characteristics: T
REG
,
T
REGXB
, T
REGYB
, T
CKSH
, and T
REGF5
. Table 65, page 52: added stepping information for
Virtex-4 FX devices.
Date Version Revisions
