Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 40

Tabl e 47 : Input Clock Tolerances

Symbol Description

Frequency

Range Value Units

Duty Cycle Input Tolerance (in %)

CLKIN_PSCLK_PULSE_RANGE_1 PSCLK only < 1 MHz 25 - 75 %

CLKIN_PSCLK_PULSE_RANGE_1_50

PSCLK and CLKIN

1 – 50 MHz

(1)

25 - 75 %

CLKIN_PSCLK_PULSE_RANGE_50_100 50 – 100 MHz

(1)

30 - 70 %

CLKIN_PSCLK_PULSE_RANGE_100_200 100 – 200 MHz

(1)

40 - 60 %

CLKIN_PSCLK_PULSE_RANGE_200_400 200 – 400 MHz

(1)

45 - 55 %

CLKIN_PSCLK_PULSE_RANGE_400 > 400 MHz 45 - 55 %

Speed Grade

-12 -11 -10

Input Clock Cycle-Cycle Jitter (Low Frequency Mode)

CLKIN_CYC_JITT_DLL_LF CLKIN (using DLL outputs)

(2,5,6)

±300 ±300 ±345 ps

CLKIN_CYC_JITT_FX_LF CLKIN (using DFS outputs)

(3)

±300 ±300 ±345 ps

Input Clock Cycle-Cycle Jitter (High Frequency Mode)

CLKIN_CYC_JITT_DLL_HF CLKIN (using DLL outputs)

(2,5,6)

±150 ±150 ±173 ps

CLKIN_CYC_JITT_FX_HF CLKIN (using DFS outputs)

(3)

±150 ±150 ±173 ps

Input Clock Period Jitter (Low Frequency Mode)

CLKIN_PER_JITT_DLL_LF CLKIN (using DLL outputs)

(2,5,6)

±1.0 ±1.0 ±1.15 ns

CLKIN_PER_JITT_FX_LF CLKIN (using DFS outputs)

(3)

±1.0 ±1.0 ±1.15 ns

Input Clock Period Jitter (High Frequency Mode)

CLKIN_PER_JITT_DLL_HF CLKIN (using DLL outputs)

(2,5,6)

±1.0 ±1.0 ±1.15 ns

CLKIN_PER_JITT_FX_HF CLKIN (using DFS outputs)

(3)

±1.0 ±1.0 ±1.15 ns

Feedback Clock Path Delay Variation

CLKFB_DELAY_VAR_EXT CLKFB off-chip feedback ±1.0 ±1.0 ±1.15 ns

Notes:

1. For boundary frequencies, use the more restrictive specifications.

2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.

4. If both DLL and DFS outputs are used, follow the more restrictive specifications.

5. The DCM must be reset if the clock input clock stops for more than 100 ms.

6. These values also apply when using both DLL and DFS outputs.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 41

Output Clock Jitter

Output Clock Phase Alignment

Tabl e 48 : Output Clock Jitter

Description Symbol Constraints

Speed Grade

Units-12 -11 -10

Clock Synthesis Period Jitter

CLK0 CLKOUT_PER_JITT_0 ±100 ±100 ±100 ps

CLK90 CLKOUT_PER_JITT_90 ±150 ±150 ±150 ps

CLK180 CLKOUT_PER_JITT_180 ±150 ±150 ±150 ps

CLK270 CLKOUT_PER_JITT_270 ±150 ±150 ±150 ps

CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ±200 ±200 ±200 ps

CLKDV (integer division) CLKOUT_PER_JITT_DV1 ±150 ±150 ±150 ps

CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ±300 ±300 ±300 ps

CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note (2) Note (2) Note (2) ps

Notes:

1. PMCD outputs are not included in this table because they do not introduce jitter.

2. Values for this parameter are available from the architecture wizard.

Tabl e 49 : Output Clock Phase Alignment

Description Symbol Constraints

Speed Grade

Units-12 -11 -10

Phase Offset Between CLKIN and CLKFB

CLKIN / CLKFB CLKIN_CLKFB_PHASE ±120 ±120 ±120 ps

Phase Offset Between Any DCM Outputs

All CLK outputs CLKOUT_PHASE ±140 ±140 ±140 ps

Duty Cycle Precision

DLL outputs

(1)

CLKOUT_DUTY_CYCLE_DLL

(3,4)

±150 ±150 ±150 ps

DFS outputs

(2)

CLKOUT_DUTY_CYCLE_FX

(4)

±200 ±200 ±200 ps

Notes:

1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.

3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION=TRUE.

4. The measured value includes the duty cycle distortion of the global clock tree.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 42

Tabl e 50 : Miscellaneous Timing Parameters

Symbol Description

Speed Grade

Units-12 -11 -10

Time Required to Achieve LOCK

T_LOCK_DLL_240 DLL output – Frequency range > 240 MHz

(2)

20 20 20 µs

T_LOCK_DLL_120_240 DLL output – Frequency range 120 - 240 MHz

(1,2)

63 63 63 µs

T_LOCK_DLL_60_120 DLL output – Frequency range 60 - 120 MHz

(1,2)

225 225 225 µs

T_LOCK_DLL_50_60 DLL output – Frequency range 50 - 60 MHz

(1,2)

325 325 325 µs

T_LOCK_DLL_40_50 DLL output – Frequency range 40 - 50 MHz

(1,2)

500 500 500 µs

T_LOCK_DLL_30_40 DLL output – Frequency range 30 - 40 MHz

(1,2)

900 900 900 µs

T_LOCK_DLL_24_30 DLL output – Frequency range 24 - 30 MHz

(1,2)

1250 1250 1250 µs

T_LOCK_DLL_30 DLL output – Frequency range < 30 MHz

(2)

1250 1250 1250 µs

T_LOCK_FX_MAX DFS outputs

(3)

10 10 10 ms

T_LOCK_DLL_FINE_SHIFT Multiplication factor for DLL lock time with Fine Shift 2 2 2

Fine Phase Shifting

FINE_SHIFT_RANGE_MS Absolute shifting range in maximum speed mode 7 7 7 ns

FINE_SHIFT_RANGE_MR Absolute shifting range in maximum range mode 10 10 10 ns

Delay Lines

DCM_TAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 5 5 5 ps

DCM_TAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 40 40 40 ps

DCM_TAP_MR_MIN Tap delay resolution (Min) in maximum range mode 10 10 10 ps

DCM_TAP_MR_MAX Tap delay resolution (Max) in maximum range mode 60 60 60 ps

Input Signal Requirements

DCM_RESET

(4)

Minimum duration that RST must be held asserted

200 200 200 ms

Maximum duration that RST can be held asserted

(5)

10 10 10 sec

DCM_INPUT_CLOCK_STOP

Maximum duration that CLKIN and CLKFB can be

stopped

(6,7)

100 100 100 ms

Notes:

1. For boundary frequencies, choose the higher delay.

2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.

4. CLKIN must be present and stable during the DCM_RESET.

5. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support

of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.

6. For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped

clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support

longer durations of stopped clocks.

7. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.

Part #	XC4VFX100-11FF1152I
Description	FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1152FCBGA - Trays
Category	IC
Availability	In Stock
Qty	2

XC4VFX100-11FF1152I

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