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XC4VFX100-11FF1152I

Part # XC4VFX100-11FF1152I
Description FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1152FCBGA - Trays
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $5,300.33071
Manufacturer Available Qty
Xilinx
Date Code: 1105
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 34
Tabl e 41 : FIFO Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
Sequential Delays
T
FCKO_DO
Clock CLK to DO output
(2)
0.72 0.80 0.92 ns, Max
T
FCKO_FLAGS
Clock CLK to FIFO flags outputs
(3)
0.93 1.04 1.19 ns, Max
T
FCKO_POINTERS
Clock CLK to FIFO pointer outputs
(4)
1.16 1.29 1.48 ns, Max
Setup and Hold Times Before Clock CLK
T
FDCK_DI
/ T
FCKD_DI
DI input
(5)
0.18
0.26
0.20
0.28
0.23
0.33
ns, Min
T
FCCK_EN
/ T
FCKC_EN
Enable inputs
(6)
0.66
0.26
0.73
0.28
0.84
0.33
ns, Min
Reset Delays
T
FCO_FLAGS
Reset RST to FLAGS
(7)
1.32 1.46 1.68 ns, Max
Maximum Frequency
F
MAX
FIFO in all modes 500.00 450.45 400.00 MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. T
FCKO_DO
includes parity output (T
FCKO_DOP
).
3. T
FCKO_FLAGS
includes the following parameters: T
FCKO_AEMPTY
, T
FCKO_AFULL
, T
FCKO_EMPTY
, T
FCKO_FULL
, T
FCKO_RDERR
, T
FCKO_WRERR.
4. T
FCKO_POINTERS
includes both T
FCKO_RDCOUNT
and T
FCKO_WRCOUNT.
5. T
FDCK_DI
includes parity inputs (T
FDCK_DIP
).
6. T
FCCK_EN
includes both WRITE and READ enable.
7. T
FCO_FLAGS
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT.
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 35
XtremeDSP™ Switching Characteristics
Tabl e 42 : XtremeDSP Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
Setup and Hold of CE Pins
T
DSPCCK_CE
/ T
DSPCKC_CE
Setup/Hold of all CE inputs of the DSP48 slice
0.39
0.09
0.43
0.10
0.49
0.12
ns
T
DSPCCK_RST
/ T
DSPCKC_RST
Setup/Hold of all RST inputs of the DSP48 slice
0.32
0.09
0.36
0.10
0.40
0.12
ns
Setup and Hold Times of Data
T
DSPDCK_{AA, BB, CC}
/
T
DSPCKD_{AA, BB, CC}
Setup/Hold of {A, B, C} input to {A, B, C} register
0.25
0.23
0.28
0.26
0.32
0.29
ns
T
DSPDCK_{AM, BM}
/
T
DSPCKD_{AM, BM}
Setup/Hold of {A, B} input to M register
1.82
0.00
2.03
0.00
2.28
0.00
ns
Sequential Delays
T
DSPCKO_PP
Clock to out from P register to P output 0.64 0.71 0.79 ns
T
DSPCKO_PM
Clock to out from M register to P output 2.38 2.65 2.98 ns
Combinatorial
T
DSPDO_{AP, BP}L
{A, B} input to P output
(LEGACY_MODE = MULT18X18)
3.53 3.92 4.41 ns
Maximum Frequency
F
MAX
From {A, B} register to P register
(LEGACY_MODE = MULT18X18)
317.46 285.71 253.94 MHz
Fully Pipelined 500.00 450.05 400.00 MHz
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 36
Configuration Switching Characteristics
Tabl e 43 : Configuration Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
Power-up Timing Characteristics
T
CONFIG
(1,2)
Maximum time to configure device after
V
CCINT
has been applied.
10 10 10 minutes
T
PL
Program Latency 0.5 0.5 0.5
µs/frame,
Max
T
POR
Power-on-Reset T
PL
+10 T
PL
+10 T
PL
+10 ms, Max
T
ICCK
CCLK (output) delay 500 500 500 ns, Min
T
PROGRAM
Program Pulse Width 300 300 300 ns, Min
Master/Slave Serial Mode Programming Switching
T
DCC
/ T
CCD
DIN Setup/Hold, slave mode
0.5
1.0
0.5
1.0
0.5
1.0
ns, Min
T
DSCK
/ T
SCKD
DIN Setup/Hold, master mode
0.5
1.0
0.5
1.0
0.5
1.0
ns, Min
T
CCO
DOUT 7.5 7.5 7.5 ns, Max
T
CCH
High Time 2.0 2.0 2.0 ns, Min
T
CCL
Low Time 2.0 2.0 2.0 ns, Min
F
CC_SERIAL
Maximum Frequency, master mode with
respect to nominal CCLK.
100 100 100 MHz, Max
F
MAX_SLAVE
/ F
MAX_ICAP
Maximum Frequency, slave mode external
CCLK
100 100 100 MHz, Max
F
MCCTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50 ±50 ±50 %
SelectMAP Mode Programming Switching
T
SMDCC
/ T
SMCCD
SelectMAP Data Setup/Hold
2.0
0.0
2.0
0.0
2.0
0.0
ns, Min
T
SMCSCC
/ T
SMCCCS
CS_B Setup/Hold
1.0
0.5
1.0
0.5
1.0
0.5
ns, Min
T
SMCCW
/ T
SMWCC
RDWR_B Setup/Hold
6.0
1.0
6.0
1.0
6.0
1.0
ns, Min
T
SMCKBY
BUSY Propagation Delay 8.0 8.0 8.0 ns, Max
F
CC_SELECTMAP
Maximum Frequency, master mode with
respect to nominal CCLK.
100 100 100 MHz, Max
F
MAX_SELECTMAP
Maximum Configuration Frequency, slave
mode external CCLK
100 100 100 MHz, Max
F
MAX_READBACK
Maximum Readback Frequency 80 80 80 MHz, Max
F
MCCTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50 ±50 ±50 %
T
SMCO
SelectMAP Readback Clock-to-Out 8.0 8.0 8.0 ns, Max
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