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XC4VFX100-11FF1152I

Part # XC4VFX100-11FF1152I
Description FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1152FCBGA - Trays
Category IC
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Xilinx
Date Code: 1105
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 31
CLB Switching Characteristics
Tabl e 37 : CLB Switching Characteristics
Symbol Description
Speed Grade
Units
-12 -11 -10
XC4VFX
(2)
XC4VLX/SX
ALL DEVICES
Combinatorial Delays
T
ILO
4-input function: F/G inputs to X/Y outputs 0.15 0.15 0.17 0.20 ns, Max
T
IF5
5-input function: F/G inputs to F5 output 0.36 0.35 0.40 0.46 ns, Max
T
IF5X
5-input function: F/G inputs to X output 0.44 0.43 0.49 0.57 ns, Max
T
IF6Y
FXINA or FXINB inputs to YMUX output 0.30 0.30 0.34 0.39 ns, Max
T
INAFX
FXINA input to FX output via MUXFX 0.21 0.21 0.23 0.27 ns, Max
T
INBFX
FXINB input to FX output via MUXFX 0.21 0.20 0.23 0.26 ns, Max
T
BXX
BX input to XMUX output 0.59 0.58 0.65 0.76 ns, Max
T
BYY
BY input to YMUX output 0.43 0.43 0.48 0.56 ns, Max
T
BXCY
BX input to C
OUT
output – Getting into carry chain
(3)
0.60 0.59 0.66 0.78 ns, Max
T
BYCY
BY input to C
OUT
output – Getting into carry chain
(3)
0.49 0.48 0.54 0.63 ns, Max
T
BYP
C
IN
input to C
OUT
output – Carry chain delay
(3)
0.07 0.07 0.08 0.09 ns, Max
T
OPCYF
F input to C
OUT
output – Getting out from carry chain
(3)
0.45 0.44 0.50 0.58 ns, Max
T
OPCYG
G input to C
OUT
output – Getting out from carry chain
(3)
0.44 0.43 0.48 0.57 ns, Max
Sequential Delays
T
CKO
FF Clock CLK to XQ/YQ outputs 0.28 0.28 0.31 0.36 ns, Max
T
CKLO
Latch Clock CLK to XQ/YQ outputs 0.37 0.36 0.41 0.48 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
DICK
/ T
CKDI
BX/BY inputs
0.36
–0.09
0.36
–0.09
0.40
–0.09
0.47
–0.09
ns, Min
T
CECK
/ T
CKCE
CE input
0.58
–0.16
0.57
–0.16
0.64
–0.16
0.75
–0.16
ns, Min
T
FXCK
/ T
CKFX
FXINA/FXINB inputs
0.42
–0.14
0.41
–0.14
0.46
–0.14
0.54
–0.14
ns, Min
T
SRCK
/ T
CKSR
SR/BY inputs (synchronous)
1.04
–0.74
1.02
–0.73
1.15
–0.73
1.35
–0.73
ns, Min
T
CINCK
/ T
CKCIN
C
IN
Data Inputs (DI) – Getting out from carry chain
(3)
0.52
–0.23
0.51
–0.23
0.57
–0.23
0.67
–0.23
ns, Min
Set/Reset
T
RPW
Minimum Pulse Width, SR/BY inputs 0.54 0.53 0.59 0.70 ns, Min
T
RQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
1.05 1.03 1.15 1.35 ns, Max
F
TOG
Toggle Frequency (MHz) (for export control) 1181 1205 1205
(4)
1028 MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX
-12 column.
3. These items are of interest for Carry Chain applications.
4. XC4VFX -11 devices are 1181 MHz.
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 32
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Tabl e 38 : CLB Distributed RAM Switching Characteristics
Symbol Description
Speed Grade
Units
-12 -11 -10
XC4VFX
(2)
XC4VLX/SX
ALL DEVICES
Sequential Delays
T
SHCKO
Clock CLK to X outputs (WE active)
(3)
1.61 1.58 1.77 2.08 ns, Max
T
SHCKOF5
Clock CLK to F5 output (WE active) 1.53 1.50 1.69 1.98 ns, Max
Setup and Hold Times Before/After Clock CLK
T
DS
/ T
DH
BX/BY data inputs (DI)
1.26
–0.90
1.23
–0.88
1.46
–0.88
1.80
–0.88
ns, Min
T
AS
/ T
AH
F/G address inputs
0.88
–0.37
0.86
–0.37
0.97
–0.34
1.13
–0.29
ns, Min
T
WS
/ T
WH
WE input (SR)
1.10
–0.48
1.08
–0.47
1.21
–0.47
1.42
–0.47
ns, Min
Clock CLK
T
WPH
Minimum Pulse Width, High 0.53 0.52 0.59 0.69 ns, Min
T
WPL
Minimum Pulse Width, Low 0.55 0.54 0.60 0.70 ns, Min
T
WC
Minimum clock period to meet address write cycle time 0.76 0.74 0.84 0.98 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3. T
SHCKO
also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
Tabl e 39 : CLB Shift Register Switching Characteristics
Symbol Description
Speed Grade
Units
-12 -11 -10
XC4VFX
(2)
XC4VLX/SX XC4VFX
(3)
XC4VLX/SX
ALL
Sequential Delays
T
REG
Clock CLK to X/Y outputs 2.12 2.08 2.19 2.19 2.57 ns, Max
T
REGXB
Clock CLK to XB output via MC15 LUT output 1.83 1.73 1.90 1.84 2.16 ns, Max
T
REGYB
Clock CLK to YB output via MC15 LUT output 1.84 1.74 1.92 1.85 2.17 ns, Max
T
CKSH
Clock CLK to Shiftout 1.70 1.60 1.76 1.70 1.99 ns, Max
T
REGF5
Clock CLK to F5 output 2.05 2.01 2.11 2.11 2.47 ns, Max
Setup and Hold Times Before/After Clock CLK
T
WS
/ T
WH
WE input (SR)
0.87
–0.76
0.85
–0.76
0.96
–0.70
0.96
–0.70
1.12
–0.62
ns, Min
T
DS
/ T
DH
BX/BY data inputs (DI)
1.28
–1.12
1.25
–1.11
1.45
–1.11
1.45
–1.11
1.75
–1.11
ns, Min
Clock CLK
T
WPH
Minimum Pulse Width, High 0.53 0.52 0.59 0.59 0.69 ns, Min
T
WPL
Minimum Pulse Width, Low 0.55 0.54 0.60 0.60 0.70 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3. The values in this column apply to all XC4VFX -11 parts.
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009 www.xilinx.com
Product Specification 33
Block RAM and FIFO Switching Characteristics
Tabl e 40 : Block RAM Switching Characteristics
Symbol Description
Speed Grade
Units-12 -11 -10
Sequential Delays
T
RCKO_DORA
Clock CLK to DOUT output (without output register)
(2)
1.65 1.83 2.10 ns, Max
Clock CLK to DOUT output with ECC
(without output register)
3.00 3.33 3.83 ns, Max
T
RCKO_DOA
Clock CLK to DOUT output (with output register)
(3)
0.72 0.80 0.92 ns, Max
Clock CLK to DOUT output with ECC (with output
register)
2.00 2.20 2.50 ns, Max
Setup and Hold Times Before Clock CLK
T
RCCK_ADDR
/ T
RCKC_ADDR
ADDR inputs
0.34
0.26
0.37
0.28
0.43
0.33
ns, Min
T
RDCK_DI
/ T
RCKD_DI
DIN inputs
(4)
0.18
0.26
0.20
0.28
0.23
0.33
ns, Min
T
RCCK_EN
/ T
RCKC_EN
EN input
(5)
0.41
0.26
0.45
0.28
0.52
0.33
ns, Min
T
RCCK_REGCE
/T
RCKC_REGCE
CE input of output register
0.25
0.26
0.27
0.28
0.32
0.33
ns, Min
T
RCCK_SSR
/ T
RCKC_SSR
RST input
0.25
0.26
0.27
0.28
0.32
0.33
ns, Min
T
RCCK_WE
/ T
RCKC_WE
WEN input
0.59
0.26
0.65
0.28
0.75
0.33
ns, Min
Maximum Frequency
F
MAX
Write first and no change mode 500.00 450.45 400.00 MHz
F
MAX
Read first mode 500.00 450.45 400.00 MHz
CLK-to-CLK Read first mode 500.00 450.45 400.00 MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. T
RCKO_DORA
includes T
RCKO_DOWA
, T
RCKO_DOPAR
, and T
RCKO_DOPAW
as well as the B port equivalent timing parameters.
3. T
RCKO_DOA
includes T
RCKO_DOPA
as well as the B port equivalent timing parameters.
4. T
RCKO_DI
includes both A and B inputs as well as the parity inputs of A and B.
5. Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable
during the specified set-up time. Do not create an asynchronous input on an enabled port address.
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