



SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007

www.ti.com

APPLICATION INFORMATION

The UCCx946 supervisory circuit provides accurate reset and watchdog functions for a variety of

microprocessor applications. The reset circuit prevents the microprocessor from executing code during

undervoltage conditions, typically during power-up and power-down. In order to prevent erratic operation in the

presence of noise, voltage glitches where voltage amplitude and time duration are less than the values specified

in Figure 1 are ignored.

100

110 120 130 140 150 160 170 180

100

120

180

140

160

200

Figure 1.

OVERDRIVE VOLTAGE WITH RESPECT TO

RESET THRESHOLD

DELAY TO OUTPUT LOW ON R

ESB

− Overdrive Voltage − mV

DELAY

− Delay Time − µs

Senses Glitch,

RES

Goes Low for Reset Period

Glitches

Ignored,

RESB

Remains

High

The watchdog circuit monitors the microprocessor’s activity, if the microprocessor does not toggle WDI during

the programmable watchdog period WDO

goes low, alerting the microprocessor’s interrupt of a fault. The WDO

pin is typically connected to the non-maskable input of the microprocessor so that an error recovery routine can

be executed.





SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007

www.ti.com

APPLICATION INFORMATION

PROGRAMMING THE RESET VOLTAGE AND RESET PERIOD

The UCCx946 allows the reset trip voltage to be programmed with two external resistors. In most applications

VDD is monitored by the reset circuit, however, the design allows voltages other than VDD to be monitored.

Referring to Figure 2, the voltage below which reset is asserted is determined by:

RESET

+ 1.235

R1 ) R2

In order to keep quiescent currents low, resistor values in the megaohm range can be used for R1 and R2. A

manual reset can be easily implemented by connecting a momentary push switch in parallel with R2. RES

ensured to be low with VDD voltages as low as 1 V.

UDG−98002

WDI

VDD

POWER TO

CIRCUITRY

WDO

GND

EDGE DETECT

WATCHDOG

TIMING

100 mV

RTH

400 nA

POWER

ON RESET

VDD

RESET

NMI

I/O

RES

−

1.235 V

400 nA

1.235 V

CLK

CLR

8−BIT

COUNTER

Figure 2. Typical Application Diagram

(1)





SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007

www.ti.com

APPLICATION INFORMATION

Once VDD rises above the programmed threshold, RES remains low for the reset period defined by:

+ 3.125 C

where T

is time in milliseconds and C

is capacitance in nanofarads. C

is charged with a precision current

source of 400 nA, a high-quality, low-leakage capacitor (such as an NPO ceramic) should be used to maintain

timing tolerances. Figure 3 illustrates the voltage levels and timings associated with the reset circuit.

UDG−97067

t1: VDD > 1 V, RES is ensured low.

t2: VDD > programmed threshold, RES

remains low for TRP.

t3: T

expires, RES

pulls high.

t4: Voltage glitch occurs, but is filtered at the RTH pin, RES

remains high.

t5: Voltage glitch occurs whose magnitude and duration is greater than the RTH filter, RES

is asserted for TRP.

t6: On completion of the TRP pulse the RTH voltage has returned and RES

is pulled high.

t7: VDD dips below threshold (minus hysteresis), RES

is asserted.

Figure 3. Reset Circuit Timings

(2)

Part #	UCC2946D
Description	MICRO SUPER W/ WATCHDOG TIMER- Rail/Tube
Category	IC
Availability	In Stock
Qty	385

Qty	Price
1 - 80	$2.76393
81 - 161	$2.19858
162 - 242	$2.07295
243 - 323	$1.92638
324 +	$1.71699

Manufacturer	Available	Qty
UNITRODE	Freelance Stock: 15 Ships Immediately
UNITRODE	Freelance Stock: 370 Ships Immediately

UCC2946D

Related Items

Technical Document