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UC2854BQ

Part # UC2854BQ
Description IC PFC CTRLR AVERAGE CURR 20PLCC
Category IC
Availability In Stock
Qty 20
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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 
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
  

1
www.ti.com
FEATURES
D
Controls Boost PWM to Near-Unity Power
Factor
D Limits Line Current Distortion To < 3%
D World-Wide Operation Without Switches
D Accurate Power Limiting
D Fixed-Frequency Average Current-Mode
Control
D High Bandwidth (5 MHz), Low-Offset Current
Amplifier
D Integrated Current- and Voltage Amplifier
Output Clamps
D Multiplier Improvements: Linearity, 500 mV
V
AC
Offset (Eliminates External Resistor), 0 V
to 5 V Multout Common-Mode Range
D V
REF
GOOD Comparator
D Faster and Improved Accuracy ENABLE
Comparator
D UVLO Options (16 V/10 V or 10.5 V/10 V)
D 300-µA Start-Up Supply Current
BLOCK DIAGRAM
DESCRIPTION
The UC3854A/B products are pin compatible
enhanced versions of the UC3854. Like the
UC3854, these products provide all of the
functions necessary for active power factor
corrected preregulators. The controller achieves
near unity power factor by shaping the AC input
line current waveform to correspond to the AC
input line voltage. To do this the UC3854A/B uses
average current mode control. Average current
mode control maintains stable, low distortion
sinusoidal line current without the need for slope
compensation, unlike peak current mode control.
A 1% 7.5 V reference, fixed frequency oscillator,
PWM, voltage amplifier with soft-start, line voltage
feedforward (V
RMS
squarer), input supply voltage
clamp, and over current comparator round out the
list of features.
Available in the 16-pin N (PDIP), DW (SOIC-
Wide), and J (CDIP) and 20-pin Q (PLCC)
package. See ordering information on page 3 for
availability by temperature range.
UDG−03110
10
11
6
8
15
1
16
ENA
VSENSE
IAC
VRMS
VCC
GND
GTDRV
2.65 V / 2.15 V
3 V
7
VAO
13
SS
X
2
A
B
C
(A) 16 V / 10 V
(B) 10.5 V / 10 V
5
MOUT
4
ISENSE
3
CAO
14
CT
OSC
12
RSET
SQ
R
R
2
PKLMT
20 V
IC
POWER
7.5 V REF
9
REF
RUN
7.1 V
RUN
V
CC
14 µA
I
MOUT
+
A B
C
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#'$#1  "** (""!'#'$,
Copyright 2003, Texas Instruments Incorporated
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 
 
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
2
www.ti.com
DESCRIPTION (continued)
The UC3854A/B products improve upon the UC3854 by offering a wide bandwidth, low offset current amplifier,
a faster responding and improved accuracy enable comparator, a VREF GOOD comparator, UVLO threshold
options (16 V/10 V for offline, 10.5 V/10 V for startup from an auxiliary 12 V regulator), lower startup supply
current, and an enhanced multiply/divide circuit. New features like the amplifier output clamps, improved
amplifier current sinking capability, and low offset VAC pin reduce the external component count while improving
performance. Improved common mode input range of the multiplier output/current amplifier input allow the
designer greater flexibility in choosing a method for current sensing. Unlike its predecessor, R
SET
controls only
oscillator charging current and has no effect on clamping the maximum multiplier output current. This current
is now clamped to a maximum of 2 × I
AC
at all times which simplifies the design process and provides foldback
power limiting during brownout and extreme low line conditions.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UCX854A, UCX854B UNIT
Supply voltage, V
CC
22 V
GTDRV current, I
GTDRV
Continuous 0.5 A
GTDRV Current, I
GTDRV
50% duty cycle 1.5 A
Input voltage
VSENSE, VRMS
,
ISENSE MOUT 11 V
Input voltage
PKLMT 5 V
Input current RSET, IAC, PKLMT, ENA 10 mA
Power dissipation 1 W
Junction temperature, T
J
−55 to 150
Storage temperature, T
stg
−65 to 150
°C
Lead temperature, T
sol,
1,6 mm (1/16 inch) from case for 10 seconds 300
C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into and negative out of, the specified terminal. ENA input is internally clamped to approximately 10 V.
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
Supply voltage, V
CC
10 20 V
UC1854X −55 125
Operating junction temperature, T
J
UC2854X −40 85
°C
Operating junction temperature, T
J
UC3854X 0 70
C

 
 
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
3
www.ti.com
PACKAGE DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
PKLMT
CAO
ISENSE
MOUT
IAC
VAO
VRMS
GTDRV
VCC
CT
SS
RSET
VSENSE
ENA
VREF
J, N and DW PACKAGES
(TOP VIEW)
5
4
6
7
8
18
17
16
15
14
ISENSE
CAOUT
N/C
MOUT
IAC
CT
SS
N/C
RSET
VSENSE
3 2 1 20 19
9 10 11 12 13
PKLMT
GND
N/C
GTDRV
VCC
VAO
VRMS
NC
VREF
ENA
Q PACKAGE
(TOP VIEW)
N/C − No connection
ORDERING INFORMATION
UVLO
UVLO
PART NUMBERS
T
A
UVLO
TURN-ON
(V)
UVLO
TURN-OFF
(V)
CDIP−16
(J)
PDIP−16
(N)
SOIC−16
(DW)
PLCC−20
(Q)
−55°C to 125°C
16 10
−55°C to 125°C
10.5 10 UC1854BJ
−40°C to 85°C
16 10 UC2854AJ UC2854AN UC2854ADW UC2854AQ
−40°C to 85°C
10.5 10 UC2854BJ UC2854BN UC2854BDW UC2854BQ
0°C to 70°C
16 10 UC3854AN UC3854ADW
0°C to 70°C
10.5 10 UC3854BN UC3854BDW
(1)
The DW and Q packages are available taped and reeled. Add TR suffix to device type (e.g. UC2854ADWTR) to order quantities of 2,000
devices per reel for the DW package and 1,000 devices per reel for the Q package.
THERMAL RESISTANCE
PACKAGED DEVICES
RESISTANCES
CDIP−16
(J)
PDIP−16
(N)
SOP−16
(DW)
PLCC−20
(Q)
θ
JC
(°C/W) 28
(2)
45 27 34
θ
JA
(°C/W) 80−120 90
(3)
50−130
(3)
43−75
(3)
(2)
θ
JC
data values stated are derived from MIL-STD-1835B which states “the baseline values shown are worst case (mean +2s) for a 60 × 60
mil microcircuit device silicon die and applicable for devices with die sizes up to 14,400 square mils. For device die sizes greater than
14,400 square mils use the following values, dual-in-line, 11°C/W; flat pack and pin grid array, 10°C/W.
(3)
θ
JA
(junction-to-ambient) applies to devices mounted to five square inch FR4 PC board with one ounce copper where noted. When
resitance range is given, lower values are for five square inch aluminum PC board. Test PWB is 0.062 inches thick and typically uses
0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land are at the
end of each trace.
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