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UC2715D

Part # UC2715D
Description COMPLEMENTARY SWITCH FET DRVRS - Rail/Tube
Category IC
Availability In Stock
Qty 185
Qty Price
1 - 38 $1.73350
39 - 77 $1.37892
78 - 116 $1.30013
117 - 155 $1.20820
156 + $1.07687
Manufacturer Available Qty
UNITRODE
Date Code: 0022
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

6
5
7
8
INPUT
T1
T2
ENBL
S
Q
R
TIMER
V
REF
S
Q
R
TIMER
V
REF
50ns ±500ns
50ns ±500ns
5V
ENBL
V
CC
3V
GND
BIAS
1.4V
ENABLE
UC1714
ONLY
4 AUX
2
PWR
1 VCC
LOGIC
GATES
TIMER
REF
3 GND
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
Complementary Switch FET Drivers
Check for Samples: UC1714, UC1715, UC2714, UC2715, UC3714, UC3715
1
FEATURES
DESCRIPTION
These two families of high speed drivers are
• Single Input (PWM and TTL Compatible)
designed to provide drive waveforms for
• High-Current Power FET Driver, 1-A Source
complementary switches. Complementary switch
and 2-A Sink
configurations are commonly used in synchronous
• Auxiliary Output FET Driver, 0.5-A Source and
rectification circuits and active clamp/reset circuits,
which provide zero voltage switching. In order to
1-A Sink
facilitate the soft switching transitions, independently
• Time Delays Between Power and Auxiliary
programmable delays between the two output
Outputs Independently Programmable from 50
waveforms are provided on these drivers. The delay
to 500-ns
pins also have true-zero voltage-sensing capability
• Time Delay or True Zero-Voltage Operation
which allows immediate activation of the
Independently Configurable for Each Output
corresponding switch when zero voltage is applied.
These devices require a PWM-type input to operate
• Switching Frequency to 1 MHz
and interface with commonly available PWM
• Typical 50-ns Propagation Delays
controllers.
• ENBL Pin Activates 220-μA Sleep Mode
In the UC1714 series, the AUX output is inverted to
• Power Output is Active-Low in Sleep Mode
allow driving a p-channel MOSFET. In the UC1715
• Synchronous Rectifier Driver
series, the two outputs are configured in a true
complementary fashion.
BLOCK DIAGRAM
Pin numbers refer to J, N and D packages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 1999–2013, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)(2)
MIN MAX UNIT
Auxiliary Driver IOH continuous –100 mA
peak –500 mA
Auxiliary Driver IOL continuous 200 mA
peak 1 A
Input Voltage Range (INPUT, ENBL) –0.3 20 V
Power Driver IOH continuous –200 mA
peak –1 A
Power Driver IOL continuous 400 mA
peak 2 A
V
CC
Supply voltage 20 V
Lead Temperature (Soldering 10 seconds) 300 °C
Operating Junction Temperature
(3)
150 °C
Storage Temperature Range –65 150 °C
(1) Consult the Packaging Section at the end of this datasheet for thermal limitations and specifications of packages.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals.
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, V
CC
= 15 V, ENBL ≥ 2 V, R
T
1 = 100 kΩ from T1 to GND, R
T
2 = 100 kΩ from T2 to GND, and −55°C
< T
A
< 125°C for the UC1714 and UC1715, –40°C < T
A
< 85°C for the UC2714 and UC2715, and 0°C < T
A
< 70°C for the
UC3714 and UC3715, T
A
= T
J
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overall
V
CC
7 20 V
I
CC
Nominal ENBL = 2 V 18 24 mA
Sleep mode ENBL = 0.8 V 200 300 µA
Power Driver (PWR)
Pre turn-on PWR output, low V
CC
= 0 V, I
OUT
= 10 mA, ENBL at 0.3 1.6 V
0.8 V
V
PWR
PWR output low, sat. INPUT = 0.8 V, I
OUT
= 40 mA 0.3 0.8
V
INPUT = 0.8 V, I
OUT
= 400 mA 2.1 2.8
V
CC
− PWR output high, sat. INPUT = 2 V, I
OUT
= −20 mA 2.1 3
V
V
PWR
INPUT = 2 V, I
OUT
= −200 mA 2.3 3
Rise time C
L
= 2200 pF 30 60 ns
Fall time C
L
= 2200 pF 25 60 ns
T1 Delay, AUX to PWR INPUT rising edge, R
T
1 = 10 kΩ
(1)
20 35 80
ns
INPUT rising edge, R
T
1 = 100 kΩ
(1)
350 500 700
PWR Prop Delay INPUT falling edge, 50%
(2)
35 100 ns
Auxiliary Driver (AUX)
V
AUX
AUX output low, sat. V
IN
= 2 V, I
OUT
= 20 mA 0.3 0.8
V
V
IN
= 2 V, I
OUT
= 200 mA 1.8 2.6
V
CC
– AUX output high, sat. V
IN
= 0.8 V, I
OUT
= –10 mA 2.1 3
V
V
AUX
V
IN
= 0.8 V, I
OUT
= –100 mA 2.3 3
Rise Time C
L
= 1000 pF 45 60 ns
(1) T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined from the
90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
(2) Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal’s transition with no
load on outputs.
2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, V
CC
= 15 V, ENBL ≥ 2 V, R
T
1 = 100 kΩ from T1 to GND, R
T
2 = 100 kΩ from T2 to GND, and −55°C
< T
A
< 125°C for the UC1714 and UC1715, –40°C < T
A
< 85°C for the UC2714 and UC2715, and 0°C < T
A
< 70°C for the
UC3714 and UC3715, T
A
= T
J
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fall Time C
L
= 1000 pF 30 60 ns
T2 Delay, PWR to AUX INPUT falling edge, R
T
2 = 10 kΩ
(1)
20 50 80
ns
INPUT falling edge, R
T
2 = 100 kΩ
(1)
250 350 550
AUX Prop Delay INPUT rising edge, 50%
(2)
35 80 ns
Enable (ENBL)
Input Threshold 0.8 1.2 2 V
I
IH
Input Current ENBL = 15 V 1 10 µA
I
IL
Input Current ENBL = 0 V –1 –10 µA
T1
Current Limit T1 = 0 V –1.6 –2 mA
Nominal Voltage at T1 2.7 3 3.3 V
Minimum T1 Delay T1 = 2.5 V
(1)
40 70 ns
T2
Current Limit T2 = 0 V –1.2 –2 mA
Nominal Voltage at T2 2.7 3 3.3 V
Minumum T2 Delay T2 = 2.5 V
(1)
50 100 ns
Input (INPUT)
Input Threshold 0.8 1.4 2 V
I
IH
Input Current INPUT = 15 V 1 10 µA
I
IL
Input Current INPUT = 0 V –5 –20 µA
DEVICE INFORMATION
DIL-8, SOIC-8; J or N, D Packages
SOIC-16; DP Package
(TOP VIEW)
(TOP VIEW)
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
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