12
UC1625
UC2625
UC3625
Fast High-Side N-Channel Driver with Transformer
Isolation
A small pulse transformer can provide excellent isolation
between the UC3625 and a high-voltage N-Channel
MOSFET while also coupling gate drive power. In this
circuit (shown in Fig. 12), a UC3724 is used as a trans-
former driver/encoder that duty-cycle modulates the
transformer with a 150kHz pulse train. The UC3725 recti-
fies this pulse train for gate drive power, demodulates the
signal, and drives the gate with over 2 amp peak current.
Both the UC3724 and the UC3725 can operate up to
500kHz if the pulse transformer is selected appropriately.
To raise the operating frequency, either lower the timing
resistor of the UC3724 (1kΩ min), lower the timing ca
-
pacitor of the UC3724 (500pF min) or both.
If there is significant capacitance between transformer
primary and secondary, together with very high output
slew rate, then it may be necessary to add clamp diodes
from the transformer primary to +12V and ground. Gen
-
eral purpose small signal switching diodes such as
1N4148 are normally adequate.
The UC3725 also has provisions for MOSFET current
limiting. Consult the UC3725 data sheet for more infor
-
mation on implementing this.
Computational Truth Table
This table shows the outputs of the gate drive and open
collector outputs for given hall input codes and direction
signals. Numbers at the top of the columns are pin
numbers.
These ICs operate with position sensor encoding that
has either one or two signals high at a time, never all low
or all high. This coding is sometimes referred to as “120°
Coding” because the coding is the same as coding with
position sensors spaced 120 magnetic degrees about
the rotor. In response to these position sense signals,
only one low-side driver will turn on (go high) and one
high-side driver will turn on (pull low) at any time.
28
7
1
6
5
4
31
2
6
7
4
8
UC3724N UC3725N
1:2
PUA
33kΩ
3
+12V
1nF5kΩ 100nF
VMOTOR
TO MOTOR
APPLICATION INFORMATION (cont.)
Figure 12. Fast high-side N-channel driver with transformer isolation.
INPUTS OUTPUTS
DIR H1 H2 H3 Low-Side High-Side
6 8 9 10 12 13 14 16 17 18
1001LHLLHH
1011LLHLHH
1010LLHHLH
1110HLLHLH
1100HLLHHL
1101LHLHHL
0101LLHHLH
0100LLHLHH
0110LHLLHH
0010LHLHHL
0011HLLHHL
0001HLLHLH
X111LLLHHH
X000LLLHHH
Table I. Computational truth table.
UDG-99047
