7
UC1625
UC2625
UC3625
S
START
clamps the output of the error amplifier, not al
-
lowing the error amplifier output voltage to exceed
S
START
regardless of input. The ramp on RC-Osc can
be applied to PWM In and compared to E/A Out. With
S
START
discharged below 0.2V and the ramp minimum
being approximately 1.0V, the PWM comparator will
keep the PWM latch cleared and the outputs off. As
S
START
rises, the PWM comparator will begin to
duty-cycle modulate the PWM latch until the error ampli
-
fier inputs overcome the clamp. This provides for a safe
and orderly motor start-up from an off or fault condition.
Tach-Out: Any change in the H1, H2, or H3 inputs loads
data from these inputs into the position sensor latches.
At the same time data is loaded, a fixed-width 5V pulse
is triggered on Tach-Out. The average value of the volt
-
age on Tach-Out is directly proportional to speed, so
this output can be used as a true tachometer for speed
feedback with an external filter or averaging circuit
which usually consists of a resistor and capacitor.
Whenever Tach-Out is high, the position latches are in-
hibited, such that during the noisiest part of the commu-
tation cycle, additional commutations are not possible.
Although this will effectively set a maximum rotational
speed, the maximum speed can be set above the high
-
est expected speed, preventing false commutation and
chatter.
V
CC
: This device operates with supplies between 10V
and 18V. Under-voltage lockout keeps all outputs off be
-
low 7.5V, insuring that the output transistors never turn
on until full drive capability is available. Bypass V
CC
to
ground with an 0.1µF ceramic capacitor. Using a 10µF
electrolytic bypass capacitor as well can be beneficial in
applications with high supply impedance.
V
REF
: This pin provides regulated 5 volts for driving
Hall-effect devices and speed control circuitry. V
REF
will
reach +5V before V
CC
enables, ensuring that Hall-effect
devices powered from V
REF
will become active before
the UC3625 drives any output. Although V
REF
is current
limited, operation over 30mA is not advised. For proper
performance V
REF
should be bypassed with at least a
0.1µF capacitor to ground.
PIN DESCRIPTIONS (cont.)
Cross Conduction Prevention
The UC3625 inserts delays to prevent cross conduction
due to overlapping drive signals. However, some thought
must always be given to cross conduction in output stage
design because no amount of dead time can prevent fast
slewing signals from coupling drive to a power device
through a parasitic capacitance.
The UC3625 contains input latches that serve as noise
blanking filters. These latches remain transparent
through any phase of a motor rotation and latch immedi
-
ately after an input transition is detected. They remain
latched for two cycles of the PWM oscillator. At a PWM
oscillator speed of 20kHz, this corresponds to 50µsto
100µs of blank time which limits maximum rotational
speed to 100kRPM for a motor with six transitions per ro
-
tation or 50kRPM for a motor with 12 transitions per rota
-
tion.
This prevents noise generated in the first 50µs of a tran
-
sition from propagating to the output transistors and
causing cross–conduction or chatter.
The UC3625 also contains six flip flops corresponding to
the six output drive signals. One of these flip flops is set
every time that an output drive signal is turned on, and
cleared two PWM oscillator cycles after that drive signal
is turned off. The output of each flip flop is used to inhibit
drive to the opposing output (see below). In this way, it is
impossible to turn on driver PUA and PDA at the same
time. It is also impossible for one of these drivers to turn
on without the other driver having been off for at least
two PWM oscillator clocks.
APPLICATION INFORMATION
EDGE
FINDER
SHIFT
REG
SQ
QR
SQ
QR
PU
PD
PULL
DOWN
PULL UP
FROM
DECODER
PWM
CLK
Figure 1. Cross conduction prevention.
