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UC2625Q

Part # UC2625Q
Description BRUSHLESS DC MTR CONTROL28-PIN PLCC
Category IC
Availability Out of Stock
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Qty Price
1 + $10.45630



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

4
UC1625
UC2625
UC3625
22
26
25
2
Quad Sel
RC-Osc
PWM In
27
28
1
E/A Out
E/A In(+)
E/A In (–)
OSC
SQ
R
S
QR
PWM CLOCK
24SSTART
3ISENSE
4ISENSE1
5ISENSE2
19VCC
23OV-Coast
6Dir
7Speed-In
2X
2.5V 250
2.9V
Q1
10µA
3.1V
9V
DIRECTION
LATCH
0.25V
PWM CLOCK
8H1
9H2
L
QD
L
QD
L
QD
9H3
+5V
+5V
+5V
EDGE
DETECT
ONE
SHOT
21RC-Brake
2k
1V
DIR COAST CHOP QUAD
H2
H1
H3
BRAKE
DECODER
CROSS
CONDUCTION
PROTECTION
LATCHES
18 PUA
17 PUB
16 PUC
14 PDA
13 PDB
12 PDC
15 GND
20 Tach-Out
11 Pwr Vcc
+5V
VREF
5V
REFERENCE
PWM
CLOCK
1.75V
ABS VALUE
0.2V
BLOCK DIAGRAM
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: T
A
= 25°C; Pwr V
CC
= V
CC
= 12V;
R
OSC
=
20k to V
REF
; C
OSC
= 2nF; R
TACH
= 33k; C
TACH
= 10nF; and all outputs unloaded. T
A
= T
J
.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Miscellaneous
Output Turn-On Delay 1 µs
Output Turn-Off Delay 1 µs
UDG-99044
5
UC1625
UC2625
UC3625
Dir, Speed-In: The position decoder logic translates the
Hall signals and the Dir signal to the correct driver sig
-
nals (PUs and PDs). To prevent output stage damage,
the signal on Dir is first loaded into a direction latch,
then shifted through a two-bit register.
As long as Speed-In is less than 250mV, the direction
latch is transparent. When Speed-In is higher than
250mV, the direction latch inhibits all changes in direc
-
tion. Speed-In can be connected to Tach-Out through a
filter, so that the direction latch is only transparent when
the motor is spinning slowly, and has too little stored en
-
ergy to damage power devices.
Additional circuitry detects when the input and output of
the direction latch are different, or when the input and
output of the shift register are different, and inhibits all
output drives during that time. This can be used to allow
the motor to coast to a safe speed before reversing.
The shift register guarantees that direction can't be
changed instantaneously. The register is clocked by the
PWM oscillator, so the delay between direction changes
is always going to be between one and two oscillator pe-
riods. At 40kHz, this corresponds to a delay of between
25µs and 50µs. Regardless of output stage, 25µs dead
time should be adequate to guarantee no overlap
cross-conduction. Toggling DIR will cause an output
pulse on Tach-Out regardless of motor speed.
E/A In(+), E/A In(–), E/A Out, PWM In: E/A In(+) and
E/A In(–) are not internally committed to allow for a wide
variety of uses. They can be connected to the I
SENSE
,to
Tach-Out through a filter, to an external command volt
-
age, to a D/A converter for computer control, or to an
-
other op amp for more elegant feedback loops. The
error amplifier is compensated for unity gain stability, so
E/A Out can be tied to E/A In(–) for feedback and major
loop compensation.
E/A Out and PWM In drive the PWM comparator. For
voltage-mode PWM systems, PWM In can be connected
to RC-Osc. The PWM comparator clears the PWM latch,
commanding the outputs to chop.
The error amplifier can be biased off by connecting E/A
In(–) to a higher voltage than E/A In(+). When biased
off, E/A Out will appear to the application as a resistor to
ground. E/A Out can then be driven by an external am
-
plifier.
GND: All thresholds and outputs are referred to the
GND pin except for the PD and PU outputs.
H1, H2, H3: The three shaft-position sensor inputs con
-
sist of hysteresis comparators with input pull-up resis
-
tors. Logic thresholds meet TTL specifications and can
be driven by 5V CMOS, 12V CMOS, NMOS, or
open-collectors.
Connect these inputs to motor shaft position sensors
that are positioned 120 electrical degrees apart. If noisy
signals are expected, zener clamp and filter these inputs
with 6V zeners and an RC filter. Suggested filtering
components are 1k and 2nF. Edge skew in the filter is
not a problem, because sensors normally generate
modified Gray code with only one output changing at a
time, but rise and fall times must be shorter than 20µs
for correct tachometer operation.
Motors with 60 electrical degree position sensor coding
can be used if one or two of the position sensor signals
is inverted.
I
SENSE1
,I
SENSE2
,I
SENSE
: The current sense amplifier
has a fixed gain of approximately two. It also has a
built-in level shift of approximately 2.5V. The signal ap-
pearing on I
SENSE
is:
()
()
I V ABS I I
SENSE SENSE SENSE
=+25 2
12
.–
I
SENSE1
and I
SENSE2
are interchangeable and can be
used as differential inputs. The differential signal applied
can be as high as
±
0.5V before saturation.
If spikes are expected on I
SENSE1
or I
SENSE2
, they are
best filtered by a capacitor from I
SENSE
to ground. Fil
-
tering this way allows fast signal inversions to be cor
-
rectly processed by the absolute value circuit. The
peak-current comparator allows the PWM to enter a cur
-
rent-limit mode with current in the windings never ex
-
ceeding approximately 0.2V/R
SENSE
.
The over current
comparator provides a fail-safe shutdown in the unlikely
case of current exceeding 0.3V/R
SENSE
.
Then, soft start
is commanded, and all outputs are turned off until the
high current condition is removed. It is often essential to
use some filter driving I
SENSE1
and I
SENSE2
to reject ex
-
treme spikes and to control slew rate. Reasonable start
-
ing values for filter components might be 250 series
resistors and a 5nF capacitor between I
SENSE1
and
I
SENSE2
. Input resistors should be kept small and
matched to maintain gain accuracy.
OV-Coast: This input can be used as an over-voltage
shutdown in put, as a coast input, or both. This input
can be driven by TTL, 5V CMOS, or 12V CMOS.
PIN DESCRIPTIONS
6
UC1625
UC2625
UC3625
PDA, PDB, PDC: These outputs can drive the gates of
N-Channel power MOSFETs directly or they can drive
the bases of power Darlingtons if some form of current
limiting is used. They are meant to drive low-side power
devices in high-current output stages. Current available
from these pins can peak as high as 0.5A. These out
-
puts feature a true totem-pole output stage. Beware of
exceeding IC power dissipation limits when using these
outputs for high continuous currents. These outputs pull
high to turn a “low-side” device on (active high).
PUA, PUB, PUC: These outputs are open-collector,
high-voltage drivers that are meant to drive high-side
power devices in high-current output stages. These are
active low outputs, meaning that these outputs pull low
to command a high-side device on. These outputs can
drive low-voltage PNP Darlingtons and P-channel
MOSFETs directly, and can drive any high-voltage de
-
vice using external charge-pump techniques, trans
-
former signal coupling, cascode level-shift transistors, or
opto-isolated drive (high-speed opto devices are recom-
mended). (See applications).
PWR V
CC
: This supply pin carries the current sourced
by the PD outputs. When connecting PD outputs directly
to the bases of power Darlingtons, the PWR V
CC
pin can
be current limited with a resistor. Darlington outputs can
also be "Baker Clamped" with diodes from collectors
back to PWR V
CC
. (See Applications)
Quad Sel: The IC can chop power devices in either of
two modes, referred to as “two-quadrant” (Quad Sel low)
and “four-quadrant” (Quad Sel high). When
two-quadrant chopping, the pull-down power devices
are chopped by the output of the PWM latch while the
pull-up drivers remain on. The load will chop into one
commutation diode, and except for back-EMF, will ex
-
hibit slow discharge current and faster charge current.
Two-quadrant chopping can be more efficient than
four-quadrant.
When four-quadrant chopping, all power drivers are
chopped by the PWM latch, causing the load current to
flow into two diodes during chopping. This mode exhibits
better control of load current when current is low, and is
preferred in servo systems for equal control over accel
-
eration and deceleration. The Quad Sel input has no ef
-
fect on operation during braking.
RC-Brake: Each time the Tach-Out pulses, the capaci
-
tor tied to RC-Brake discharges from approximately
3.33V down to 1.67V through a resistor. The tachometer
pulse width is approximately T = 0.67 R
T
C
T
, where R
T
and C
T
are a resistor and capacitor from RC-Brake to
ground. Recommended values for R
T
are 10k to
500k, and recommended values for C
T
are 1nF to
100nF, allowing times between 5µs and 10ms. Best ac
-
curacy and stability are achieved with values in the cen
-
ters of those ranges.
RC-Brake also has another function. If RC-Brake pin is
pulled below the brake threshold, the IC will enter brake
mode. This mode consists of turning off all three
high-side devices, enabling all three low-side devices,
and disabling the tachometer. The only things that in
-
hibit low-side device operation in braking are
low-supply, exceeding peak current, OV-Coast com
-
mand, and the PWM comparator signal. The last of
these means that if current sense is implemented such
that the signal in the current sense amplifier is propor
-
tional to braking current, the low-side devices will brake
the motor with current control. (See applications) Sim
-
pler current sense connections will result in uncontrolled
braking and potential damage to the power devices.
RC-Osc: The UC3625 can regulate motor current using
fixed-frequency pulse width modulation (PWM). The
RC-Osc pin sets oscillator frequency by means of timing
resistor R
OSC from the RC-Osc pin to V
REF
and capaci-
tor C
OSC
from RC-Osc to Gnd. Resistors 10k to
100k and capacitors 1nF to 100nF will work best, but
frequency should always be below 500kHz. Oscillator
frequency is approximately:
()
F
RC
OSC OSC
=
2
Additional components can be added to this device to
cause it to operate as a fixed off-time PWM rather than
a fixed frequency PWM, using the RC-Osc pin to select
the monostable time constant.
The voltage on the RC-Osc pin is normally a ramp of
about 1.2V peak-to-peak, centered at approximately
1.6V. This ramp can be used for voltage-mode PWM
control, or can be used for slope compensation in cur
-
rent-mode control.
S
START
: Any time that V
CC
drops below threshold or the
sensed current exceeds the over-current threshold, the
soft-start latch is set. When set, it turns on a transistor
that pulls down on S
START
.
Normally, a capacitor is con
-
nected to this pin, and the transistor will completely dis
-
charge the capacitor. A comparator senses when the
NPN transistor has completely discharged the capacitor,
and allows the soft-start latch to clear when the fault is
removed. When the fault is removed, the soft-start ca
-
pacitor will charge from the on-chip current source.
PIN DESCRIPTIONS (cont.)
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