2–6

interrupt mask register is set, an MCU interrupt will be generated and the USB function reset (0x17) vector will appear

in the interrupt vector register (VECINT).

The function reset enable bit (FRSTE) in the USB control register (USBCTL) is used to control the extent to which

the internal logic is reset. The function reset enable bit is set to a 1 by the MCU to enable the USB reset to reset all

internal logic including the MCU. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits

will not be reset. When this bit is set, the reset output (RSTO

) signal from the device will also be active when a USB

reset occurs. This bit is not affected by USB reset.

2.2.5 USB Suspend and Resume Modes

All USB devices must support the suspend and resume modes. During the suspend mode, USB devices that are bus

powered must enter a low power suspend state. If the USB peripheral device is not bus powered, then entering the

low power suspend state is not required. A suspend condition is defined as a constant idle state on the bus for more

than 3.0ms. A USB device must actually be in the suspend state no more than 10 ms after the suspend condition is

detected. There are two ways for the TUSB3200 device to exit the suspend mode, which are 1) detection of USB

resume signaling and 2) detection of a local remote wake-up event.

2.2.5.1 USB Suspend Mode

When a suspend condition is detected on the USB, the suspend/resume logic will set the function suspend request

bit (SUSR) in the USB status register. As a result, the function suspend request interrupt (SUSR) will be generated.

To enter the low power suspend state and disable all TUSB3200 device clocks, the MCU firmware should set the idle

mode bit (IDL), which is bit 0 in the MCU power control (PCON) register. The instruction that sets the IDL bit will be

the last instruction executed before the MCU goes to idle mode. In idle mode, the MCU status is preserved. Note that

the low power suspend state is a state in which the TUSB3200 clocks are disabled and the IC will consume the least

amount of power possible.

2.2.5.2 USB Resume Mode

When the TUSB3200 is in a suspend state, any non-idle signaling on the USB will be detected by the suspend/resume

logic and device operation will be resumed. As a result of the resume signaling being detected, the TUSB3200 clocks

will be enabled, the function resume request bit (RESR) will be set, and the function resume request interrupt (RESR)

will be generated. The function resume request interrupt to the MCU will automatically clear the idle mode bit in the

PCON register. As a result, MCU operation will resume with servicing the new interrupt. After the RETI from the ISR,

the next instruction to be executed will be the one following the instruction that set the IDL bit. Note that if the low power

suspend state was not entered by setting the IDL bit, the clocks will already be enabled and the IDL bit will already

be cleared.

2.2.5.3 USB Remote Wake-up Mode

The TUSB3200 device has the capability to remotely wake-up the USB by generating resume signaling upstream.

Note that this feature must be enabled by the host software with the SET_FEATURE DEVICE_REMOTE_WAKEUP

request. The remote wake-up resume signaling should not be generated until the suspend state has been active for

at least 5 ms. In addition, the remote wake-up resume signaling must be generated for at least 1ms but for no more

than 15 ms. When the TUSB3200 is in the low power suspend state, asserting the external interrupt input (XINT

) to

the device will enable the clocks and generate the XINT interrupt. The XINT interrupt to the MCU will automatically

clear the idle mode bit in the PCON register. As a result, MCU operation will resume with servicing the new interrupt.

After the RETI from the ISR, the next instruction to be executed will be the one following the instruction that set the

IDL bit. Please note that if the low power suspend state was not entered by setting the IDL bit, the clocks will already

be enabled and the IDL bit will already be cleared. When the firmware sets the remote wake-up request bit (RWUP)

in the USB control register, the suspend/resume logic will generate the resume signaling upstream on the USB.

2.2.6 Power Supply Sequencing

Turning power supplies on and off with a mixed 5-V/3.3-V system is an important consideration. To avoid possible

damage to the TUSB3200 device, proper power sequencing is required. The turnon requirement is that the 5-V and

2–7

3.3-V power supplies should start ramping from 0 volts and reach 95 percent of the final voltage values within 25 ms

of each other. The turnoff requirement is that the 5-V and 3.3-V power supplies should start ramping from the

steady-state voltage and reach 5 percent of these values within 25 ms of each other. In addition, the difference

between the two voltages should never exceed 3.6-V while turning on or off. Normally, in a mixed voltage system,

the 3.3-V supply is generated from a voltage regulator running from the 5-V supply. A voltage regulator, such as the

Texas Instrument’s TP7133, can be used to meet these power sequencing requirements.

2.2.7 USB Transfers

The TUSB3200 device supports all the USB data transfer types, which are control, bulk, interrupt, and isochronous.

In accordance with the USB specification, endpoint zero is reserved for the control endpoint and is bidirectional. In

addition to the control endpoint, the TUSB3200 is capable of supporting up to 7 in endpoints and 7 out endpoints.

These additional endpoints can be configured as bulk, interrupt, or isochronous endpoints. The MCU handles all

control, bulk, and interrupt endpoint transactions. In addition the MCU can handle isochronous endpoint transactions,

such as a rate feedback endpoint to the host PC. However, for streaming isochronous data between the host PC and

the CODEC interface port, the DMA channels are provided.

2.2.7.1 Controls Transfers

Control transfers are used for configuration, command, and status communication between the host PC and the

TUSB3200 device. Control transfers to the TUSB3200 device use in endpoint 0 and out endpoint 0. The three types

of control transfers are control write, control write with no data stage, and control read. Note that the control endpoint

must be initialized before connecting the TUSB3200 device to the USB.

2.2.7.1.1 Control Write Transfer (Out Transfer)

The host PC uses a control write transfer to write data to the USB function. A control write transfer consists of a setup

stage transaction, at least one out data stage transaction, and an in status stage transaction.

The steps to be followed for a control write transfer are as follows:

1. MCU initializes in endpoint 0 and out endpoint 0 by programming the appropriate USB endpoint

configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer

mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the

NACK bit for both in endpoint 0 and out endpoint 0.

Setup Stage Transaction:

2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint 0.

If the data is received without an error, then the UBM will write the data to the setup data packet buffer, set

the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK handshake to the

host PC, and assert the setup stage transaction interrupt. Note that as long as the setup transaction

(SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or status stage

transactions regardless of the endpoint 0 NACK or STALL bit values.

3. The MCU services the interrupt and reads the setup data packet from the buffer then decodes the

command. If the command is not supported or valid, the MCU should set the STALL bit in the out endpoint

0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage transaction

(SETUP) bit. This will cause the device to return a STALL handshake for any data stage or status stage

transactions. After reading the data packet and decoding the command, the MCU should clear the interrupt,

which will automatically clear the setup stage transaction status bit. The MCU should also set the TOGGLE

bit in the out endpoint 0 configuration byte to a 1. For control write transfers, the PID used by the host for

the first out data packet will be a DATA1 PID and the TOGGLE bit must match.

2–8

Data Stage Transaction(s):

1. The host PC sends an out token packet followed by a data packet addressed to out endpoint 0. If the data

is received without an erro,r then the UBM will write the data to the endpoint buffer, update the data count

value, toggle the TOGGLE bit, set the NACK bit to a 1, return an ACK handshake to the host PC, and assert

the endpoint interrupt.

2. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU

first needs to obtain the data count value. After reading the data packet, the MCU should clear the interrupt

and clear the NACK bit to allow the reception of the next data packet from the host PC.

3. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NAK handshake

to the host PC. IF the STALL bit is set to a 1 when the data packet is received, the UBM simply returns A

STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then

no handshake is returned to the host PC.

Status Stage Transaction:

1. For in endpoint 0, the MCU updates the data count value to zero, sets the TOGGLE bit to 1, then clears the

NACK bit to a 0 to enable the data packet to be sent to the host PC. Note that for a status stage transaction

a null data packet with a DATA1 PID is sent to the host PC.

2. The host PC sends an in token packet addressed to in endpoint 0. After receiving the in token, the UBM

transmits a null data packet to the host PC. If the data packet is received without errors by the host PC, then

an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the NACK bit to a 1, and

assert the endpoint interrupt.

3. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK handshake

to the host PC. IF the STALL bit is set to a 1 when the in token packet is received, the UBM simply returns

a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM

prepares to retransmit the same data packet again.

2.2.7.1.2 Control Write With No Data Stage Transfer (Out Transfer)

The host PC uses a control write transfer to write data to the USB function. A control write with no data stage transfer

consists of a setup stage transaction and an in status stage transaction. For this type of transfer, the data to be written

to the USB function is contained in the two byte value field of the setup stage transaction data packet.

The steps to be followed for a control write with no data stage transfer are as follows: