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2 Description

2.1 Architectural Overview

2.1.1 Oscillator and PLL

Using an external 6-MHz crystal, the TUSB3200 derives the fundamental 48-MHz internal clock signal using an

on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated by the clock

generator and adaptive clock generator.

2.1.2 Clock Generator and Sequencer Logic

Utilizing the 48-MHz input from the PLL, the clock generator logic generates all internal clock signals, except for the

CODEC port interface master clock (MCLK) and serial clock (CSCLK) signals. The TUSB3200 internal clocks include

the 48-MHz clock, a 24-MHz clock, a 12-MHz clock and a USB clock. The USB clock also has a frequency of 12-MHz.

The USB clock is the same as the 12-MHz clock when the TUSB3200 is transmitting data and is derived from the

data when the TUSB3200 is receiving data. To derive the USB clock when receiving USB data, the TUSB3200 utilizes

an internal digital PLL (DPLL) that uses the 48-MHz clock.

The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and the USB

endpoint buffer space. The SRAM can be accessed by the MCU, USB buffer manager (UBM) or DMA channels. The

sequencer controls the access to the memory using a round robin fixed priority arbitration scheme. This basically

means that the sequencer logic generates grant signals for the MCU, UBM and DMA channels at a predetermined

fixed frequency.

2.1.3 Adaptive Clock Generator (ACG)

The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the CODEC

port interface and the CODEC device. To synchronize the sample rate conversion of data by the CODEC to the USB

frame rate, the MCLKO signal generated by the adaptive clock generator must be used. The synchronization of the

MCLKO signal to the USB frame rate is controlled by the MCU by programming the adaptive clock generator

frequency value. The MCLKO frequency is monitored by the MCU and updated as required. For asynchronous

operation, an external source can be used to generate a master clock input signal (MCLKI) to be used by the CODEC

port interface. In this scenario, the CODEC device should also use the same master clock signal (MCLKI).

2.1.4 USB Transceiver

The TUSB3200 provides an integrated transceiver for the USB port. The transceiver includes a differential output

driver, a differential input receiver and two single ended input buffers. The transceiver connects to the USB DP and

DM signal terminals.

2.1.5 USB Serial Interface Engine (SIE)

The serial interface engine logic manages the USB packet protocol requirements for the packets being received and

transmitted on the USB by the TUSB3200 device. For packets being received, the SIE decodes the packet identifier

field (PID) to determine the type of packet being received and to ensure the PID is valid. For token packets and data

packets being received, the SIE calculates the packet cycle redundancy check (CRC) and compares the value to the

CRC contained in the packet to verify that the packet was not corrupted during transmission. For token packets and

data packets being transmitted, the SIE generates the CRC that is transmitted with the packet. For packets being

transmitted, the SIE also generates the synchronization field (SYNC) that is an eight bit filed at the beginning of each

packet. In addition, the SIE generates the correct PID for all packets being transmitted. Another major function of the

SIE is the overall serial-to-parallel conversion of the data packets being received and the parallel-to-serial conversion

of the data packets being transmitted.

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2.1.6 USB Buffer Manager (UBM)

The USB buffer manager provides the control logic that interfaces the SIE to the USB endpoint buffers. One of the

major functions of the UBM is to decode the USB function address to determine if the host PC is addressing the

TUSB3200 device USB peripheral function. In addition, the endpoint address field and direction signal are decoded

to determine which particular USB endpoint is being addressed. Based on the direction of the USB transaction and

the endpoint number, the UBM will either write or read the data packet to/from the appropriate USB endpoint data

buffer.

2.1.7 USB Frame Timer

The USB frame timer logic receives the start of frame (SOF) packet from the host PC each USB frame. Each frame,

the logic stores the 11-bit frame number value from the SOF packet in a register and asserts the internal SOF signal.

The frame number register can be read by the MCU and the value can be used as a time stamp. For USB frames

in which the SOF packet is corrupted or not received, the frame timer logic will generate a pseudo start of frame

(PSOF) signal and increment the frame number register.

2.1.8 USB Suspend and Resume Logic

The USB suspend and resume logic detects suspend and resume conditions on the USB. This logic also provides

the internal signals used to control the TUSB3200 device when these conditions occur. The capability to resume

operation from a suspend condition with a locally generated remote wake-up event is also provided.

2.1.9 MCU Core

The TUSB3200 uses an 8-bit microcontroller core that is based on the industry standard 8052. The MCU is software

compatible with the 8052, 8032, 80C52, 80C53, and 87C52 MCUs. The 8052 MCU is the processing core of the

TUSB3200 and handles all USB control, interrupt and bulk endpoint transfers. In addition, the MCU can also be the

source or sink for USB isochronous endpoint transfers.

2.1.10 MCU Memory

In accordance with the industry standard 8052, the TUSB3200 MCU memory is organized into program memory,

external data memory and internal data memory. A 4K byte boot ROM is used to download the application code to

an 8K byte RAM that is mapped to the program memory space. The external data memory includes the USB endpoint

configuration blocks, USB data buffers, and memory mapped registers. The total external data memory space used

is 2K bytes. A total of 256 bytes are provided for the internal data memory.

2.1.11 USB Endpoint Configuration Blocks and Endpoint Buffer Space

The USB endpoint configuration blocks are used by the MCU to configure and operate the required USB endpoints

for a particular application. In addition to the control endpoint, the TUSB3200 supports a total of seven in endpoints

and seven out endpoints. A set of six bytes is provided for each endpoint to specify the endpoint type, buffer address,

buffer size and data packet byte count.

The USB endpoint buffer space provided is a total of 1832 bytes. The space is totally configurable by the MCU for

a particular application. Therefore, the MCU can configure each buffer based on the total number of endpoints to be

used, the maximum packet size to be used for each endpoint, and the selection of single or double buffering.

2.1.12 DMA Controller

Four DMA channels are provided to support the streaming of data for USB isochronous endpoints. Each DMA channel

can support one USB isochronous endpoint, either in or out. The DMA channels are used to stream data between

the USB endpoint data buffers and the CODEC port interface. The USB endpoint number and direction can be

programmed for each DMA channel. Also, the CODEC port interface time slots to be serviced by each DMA channel

can be programmed.

Part #	TUSB3200ACPAH
Description	USB STREAMING CONTROLLER
Category	IC
Availability	Out of Stock
Qty	0

TUSB3200ACPAH

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