1–7

1.6 Terminal Functions – Normal Mode (Continued)

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

SDA 41 I/O I

C interface serial data input/output: SDA is the bidirectional data signal for the I

C serial interface. This signal

uses a 3.3-V to 5-VTTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level shifting input buffer.

TEST 11 I Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V

TTL/LVCMOS input buffer.

XINT 17 I External interrrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. This signal

uses a 5-V compatible input buffer.

XTALI 51 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal.

XTALO 50 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal.

1.7 Terminal Functions – External MCU Mode

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

2 3.3-V Analog supply voltage

49 Analog ground

CSCLK 34 I/O CODEC port interface serial clock:CSCLK is the serial clock for the CODEC port interface used to clock the

CSYNC, CDATO, CDATI, CRESET

AND CSCHNE signals. This signal uses a 5-V compatible TTL/LVCMOS

input/output buffer.

CSYNC 35 I/O CODEC port interface frame sync: CSYNC is the frame synchronization signal for the CODEC port interface.

This signal uses a 5-V compatible TTL/LVCMOS input/output buffer.

CDATO 36 I/O CODEC port interface serial data output: See section 1.9 for details. This signal uses a 5-V compatible TTL/

LVCMOS input/output buffer.

CDATI 38 I/O CODEC port interface serial data input: See section 1.9 for details. This signal uses a 5-V compatible TTL/

LVCMOS input/output buffer.

CRESET 39 I/O CODEC port interface reset output: See section 1.9 for details. This signal uses a 5-V compatible TTL/

LVCMOS input/output buffer.

CSCHNE 40 I/O CODEC port interface secondary channel enable: See section 1.9 for details. This signal uses a 5-V

compatible TTL/LVCMOS input/output buffer.

DP 7 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair used to

connect the TUSB3200 device to the universal serial bus.

DM 8 I/O USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential pair used

to connect the TUSB3200 device to the universal serial bus.

9, 21, 37 3.3-V Digital supply voltage

DDS

27, 43 5 V-Digital supply voltage

5, 16, 33,

Digital ground

EXTEN 12 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal uses a 3.3

V TTL/LVCMOS input buffer.

MCLKI 47 I Master clock input: An input that can be used as the master clock for the CODEC port interface or the source for

MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.

MCLKI2 48 I Master clock input 2: An input that can be used as the master clock for the CODEC port interface or the source

for MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.

MCLKO 44 O Master clock output: The output of the ACG that can be used as the master clock for the CODEC port interface

and the CODEC. This signal uses a 3.3-V TTL/LVCMOS output buffer

MCLKO2 45 O Master clock output 2: An output that can be used as the master clock for the CODEC port interface and the

CODEC. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V TTL/LVCMOS

output buffer.

MCUAD0 24 I/O MCU multiplexed address/data bit 0: Multiplexed address bit 0/data bit 0 for external MCU access to the

TUSB3200 external data memory space.

1–8

1.7 Terminal Functions – External MCU Mode (Continued)

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

MCUAD1 25 I/O MCU multiplexed address/data bit 1: Multiplexed address bit 1/data bit 1 for external MCU access to the

TUSB3200 external data memory space.

MCUAD2 26 I/O MCU multiplexed address/data bit 2: Multiplexed address bit 2/data bit 2 for external MCU access to the

TUSB3200 external data memory space.

MCUAD3 28 I/O MCU multiplexed address/data bit 3: Multiplexed address bit 3/data bit 3 for external MCU access to the

TUSB3200 external data memory space.

MCUAD4 29 I/O MCU multiplexed address/data bit 4: Multiplexed address bit 4/data bit 4 for external MCU access to the

TUSB3200 external data memory space.

MCUAD5 30 I/O MCU multiplexed address/data bit 5: Multiplexed address bit 5/data bit 5 for external MCU access to the

TUSB3200 external data memory space.

MCUAD6 31 I/O MCU multiplexed address/data bit 6: Multiplexed address bit 6/data bit 6 for external MCU access to the

TUSB3200 external data memory space.

MCUAD7 32 I/O MCU multiplexed address/data bit 7: Multiplexed address bit 7/data bit 7 for external MCU access to the

TUSB3200 external data memory space.

MCUA8 14 I MCU address bit 8: Multiplexed address bit 8 for external MCU access to the TUSB3200 external data memory

space.

MCUA9 15 I MCU address bit 9: Multiplexed address bit 9 for external MCU access to the TUSB3200 external data memory

space.

MCUA10 18 I MCU address bit 10: Multiplexed address bit 10 for external MCU access to the TUSB3200 external data

memory space.

MCUALE 19 I MCU address latch enable: Address latch enable for external MCU access to the TUSB3200 external data

memory space.

MCUINTO 20 O MCU interrupt output: Interrupt output to be used for external MCU INTO input signal. All internal TUSB3200

interrupt sources are ORed together to generate this output signal.

MCURD 23 I MCU read strobe: Read strobe for external MCU read access to the TUSB3200 external data memory space.

MCUWR 22 I MCU write strobe: Write strobe for external MCU write access to the TUSB3200 external data memory space.

MRESET 10 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state. This signal

uses a 3.3-V TTL/LVCMOS input bufer.

Not Used 4 O This pin is not used in the normal mode.

PLLFILI 52 I PLL loop filter input: Input to on-chip PLL from external filter components.

PLLFILO 1 O PLL loop filter output: Output to on-chip PLL from external filter components.

PUR 6 O USB data signal plus pullup resistor connect: PUR is used to connect the pullup resistor on the DP signal to 3.3-V

or a 3-state. When the DP signal is connected to 3.3-V the host PC should detect the connection of the

TUSB3200 device to the universal serial bus. This signal uses a 3.3-V TTL/LVCMOS output buffer.

PWMO 3 O PWM output: Output of the pulse width modulation circuit. This signal uses a 3.3-V to 5-V CMOS level shifting

output buffer.

RSTO 13 O Reset output: Output that is active while the master reset input or the USB reset is active. This signal uses a 3.3-V

TTL/LVCMOS output buffer.

SCL 42 O I

C interface serial clock: SCL is the clock signal for the I

C serial interface. This signal uses a 3.3-V to 5-V TTL

level shifting open drain output buffer.

SDA 41 I/O I

C interface serial data input/output: SDA is the bidirectional data signal for the I

C serial interface. This signal

uses a 3.3-V to 5-V TTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level shifting input buffer.

TEST 11 I Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V TTL/

LVCMOS input buffer.

XINT 17 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. This signal

uses a 5-V compatible input buffer.

XTALI 51 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal.

XTALO 50 O Crystal output: Output from the on-chip oscillator to an external 6-MHz crystal.

1–9

1.8 Device Operation Modes

The EXTEN and TEST pins define the mode that the TUSB3200 will be in after reset.

MODE EXTEN TEST

Normal mode – internal MCU 0 0

External MCU mode 1 0

Factory test 0 1

Factory test 1 1

1.9 Terminal Assignments for CODEC Port Interface Modes

The CODEC port interface has eight modes of operation that support AC97, I

S, and AIC CODECs. There is also

a general-purpose mode that is not specific to a serial interface. The mode is programmed by writing to the mode

select field of the CODEC port interface configuration register 1 (CPTCNF1). The CODEC port interface terminals

CSYNC, CSCLK, CDATO, CDATI, CRESET

, and CSCHNE take on functionality appropriate to the mode

programmed as shown in the following tables.

TERMINAL

GP AIC AC ’97 v1.X AC ’97 v2.X

NO. NAME

Mode 0 Mode 1 Mode 2 Mode 3

35 CSYNC CSYNC I/O FS O SYNC O SYNC O

34 CSCLK CSCLK I/O SCLK O BIT_CLK I BIT_CLK I

36 CDATO CDATO O DOUT O SD_OUT O SD_OUT O

38 CDATI CDATI I DIN I SD_IN I SD_IN1 I

39 CRESET CRESET O RESET O RESET O RESET O

40 CSCHNE NC O FC O NC O SD_IN2 I

TERMINAL

S I

NO. NAME

Mode 4 Mode 5 Mode 6 Mode 7

35 CSYNC LRCK O LRCK O LRCK O LRCK O

34 CSCLK SCLK O SCLK O SCLK O SCLK O

36 CDATO SDOUT1 O SDOUT1 O SDOUT1 O SDOUT1 O

38 CDATI SDOUT2 O SDOUT2 O SDIN1 I SDOUT2 O

39 CRESET SDOUT3 O SDIN1 I SDIN2 I SDOUT3 O

40 CSCHNE SDIN1 I SDIN2 I SDIN3 I SDOUT4 O

NOTES: 1. Signal names and I/O direction are with respect to the TUSB3200 device. The signal names used for

the TUSB3200 terminals for the various CODEC port interface modes reflect the nomenclature used

by the CODEC devices.

2. NC indicates no connection for the terminal in a particular mode. The TUSB3200 device drives the

signal as an output for these cases.

3. The CSYNC and CSCLK signals can be programmed as either an input or an output in the

general-purpose mode.

Part #	TUSB3200ACPAH
Description	USB STREAMING CONTROLLER
Category	IC
Availability	Out of Stock
Qty	0

TUSB3200ACPAH

Related Items

Technical Document