A–40

A.5.7 Miscellaneous Registers

This section describes the memory-mapped registers used for the control and operation of miscellaneous functions

in the TUSB3200 device. The registers include the USB out endpoint interrupt register, the USB in endpoint interrupt

A.5.7.1 USB Out Endpoint Interrupt Register (OEPINT – Address FFB4h)

The USB out endpoint interrupt register contains the interrupt pending status bits for the USB out endpoints. These

bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for

diagnostic purposes only.

Bit 7 6 5 4 3 2 1 0

Mnemonic OEPI7 OEPI6 OEPI5 OEPI4 OEPI3 OEPI2 OEPI1 OEPI0

Type R R R R R R R R

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:0 OEPI(7:0) Out endpoint interrupt The out endpoint interrupt status bit for a particular USB out endpoint is set to a 1 by

the UBM when a successful completion of a transaction occurs to that out endpoint.

When a bit is set, an interrupt to the MCU will be generated and the corresponding

interrupt vector will result. The status bit will be cleared when the MCU writes to the

interrupt vector register. These bits do not apply to isochronous out endpoints.

A.5.7.2 USB In Endpoint Interrupt Register (IEPINT – Address FFB3h)

The USB in endpoint interrupt register contains the interrupt pending status bits for the USB in endpoints. These bits

do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic

purposes only.

Bit 7 6 5 4 3 2 1 0

Mnemonic IEPI7 IEPI6 IEPI5 IEPI4 IEPI3 IEPI2 IEPI1 IEPI0

Type R R R R R R R R

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:0 IEPI(7:0) In endpoint interrupt The in endpoint interrupt status bit for a particular USB in endpoint is set to a 1 by the

UBM when a successful completion of a transaction occurs to that in endpoint.

When a bit is set, an interrupt to the MCU will be generated and the corresponding

interrupt vector will result. The status bit will be cleared when the MCU writes to the

interrupt vector register. These bits do not apply to isochronous in endpoints.

A–41

A.5.7.3 Interrupt Vector Register (VECINT – Address FFB2H)

The interrupt vector register contains a 6-bit vector value that identifies the interrupt source for the INT0 input to the

MCU. All of the TUSB3200 internal interrupt sources and the external interrupt input to the device are ORed together

to generate the internal INT0 signal to the MCU. When there is not an interrupt pending, the interrupt vector value

will be set to 24h. To clear any interrupt and update the interrupt vector value to the next pending interrupt, the MCU

should simply write any value to this register. The interrupt priority is fixed in order, ranging from vector value 1Fh with

the highest priority to vector value 00h with the lowest priority.

Bit 7 6 5 4 3 2 1 0

Mnemonic — — IVEC5 IVEC4 IVEC3 IVEC2 IVEC1 IVEC0

Type R R R R R R R R

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 — Reserved Reserved for future use

6 — Reserved Reserved for future use

5:0 IVEC(5:0) Interrupt vector 00h = USB out endpoint 0

01h = USB out endpoint 1

02h = USB out endpoint 2

03h = USB out endpoint 3

04h = USB out endpoint 4

05h = USB out endpoint 5

06h = USB out endpoint 6

07h = USB out endpoint 7

08h = USB in endpoint 0

09h = USB in endpoint 1

0Ah = USB in endpoint 2

0Bh = USB in edpoint 3

0Ch = USB in endpoint 4

0Dh = USB in endpoint 5

0Eh = USB in endpoint 6

0Fh = USB in endpoint 7

10h = USB setup stage transaction over-write

11h = Reserved

12h = USB setup stage transaction

13h = USB pseudo start-of-frame

14h = USB start-of-frame

15h = USB function resume

16h = USB function suspend

17h = USB function reset

18h = C-port receive data register full

19h = C-port transmit data register empty

1Ah = Reserved

1Bh = Reserved

1Ch = I

C receive data register full

1Dh = I

C transmit data register empty

1Eh = Reserved

1Fh = External interrupt input

20h – 23h = Reserved

24h = No interrupt pending

25h – 3Fh = Reserved

A–42

A.5.7.4 Global Control Register (GLOBCTL – Address FFB1h)

The global control register contains various global control bits for the TUSB3200 device.

Bit 7 6 5 4 3 2 1 0

Mnemonic MCUCLK XINTEN PUDIS — — LPWR — CPTEN

Type R/W R/W R/W R R R/W R R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 MCUCLK MCU clock select The MCU clock select bit is used by the MCU to program the clock frequency to be

used for the MCU operation.

0b = 12 MHz and 1b = 24 MHz

6 XINTEN External interrupt enable The external interrupt enable bit is set to a 1 by the MCU to enable the use of the

external interrupt input to the TUSB3200 device.

5 PUDIS Pull-up resistor disable The pull-up resistor disable bit is set to a 1 by the MCU to disable the TUSB3200

on-chip pull-up resistors.

4 — Reserved Reserved for future use

3 — Reserved Reserved for future use

2 LPWR Low power mode disable The low power mode disable bit is used by the MCU to disable the TUSB3200

semi-low power state. When this bit is cleared to a 0, all USB functional blocks

including the USB buffers and configuration blocks are powered-down. For normal

operation, the MCU must set this bit to a 1.

1 — Reserved Reserved for future use

0 CPTEN CODEC port enable The CODEC port enable bit is set to a 1 by the MCU to enable the operation of the

CODEC port interface. Note that the CODEC port interface configuration registers

should be fully programmed before this bit is set by the MCU.

A.5.7.5 Memory Configuration Register (MEMCFG – Address FFB0h)

The memory configuration register contains various bits pertaining to the memory configuration of the TUSB3200

device.

Bit 7 6 5 4 3 2 1 0

Mnemonic MEMTYP CODESZ1 CODESZ0 REV3 REV2 REV1 REV0 SDW

Type R R R R R R R R/W

Default 1 0 1 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 MEMTYP Code memory type The code memory type bit identifies if the type of memory used for the application

program code space is ROM or RAM. For the TUSB3200, an 8K byte RAM is used

and this bit is tied to 1.

6:5 CODESZ Code space size The code space size bits identify the size of the application program code memory

space. For the TUSB3200, an 8K byte RAM is used and these bits are tied to 01b.

00b = 4K bytes, 01b = 8K bytes, 10b = 16K bytes, 11b = 32K bytes

4:1 REV IC revision The IC revision bits identify the revision of the IC.

0000b = Rev. -, 0001b = Rev. A, …, 1111b = Rev. F

0 SDW Shadow the boot ROM The shadow the boot ROM bit is set to a 1 by the MCU to switch the MCU memory

configuration from boot loader mode to normal operating mode. This should occur

after completion of the download of the application program code by the boot ROM.

Part #	TUSB3200ACPAH
Description	USB STREAMING CONTROLLER
Category	IC
Availability	Out of Stock
Qty	0

TUSB3200ACPAH

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