A–31

A.5.4.3 CODEC port interface configuration register 3 (CPTCNF2 – Address FFDEh)

The CODEC port interface configuration register 3 is used to store various control bits for the CODEC port interface

operation.

Bit 7 6 5 4 3 2 1 0

Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 1 1 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 DDLY Data delay The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of

the serial data output and input signals in reference to the leading edge of the

CSYNC signal. The MCU should clear this bit to a 0 for no delay between these

signals.

6 TRSEN 3-State enable The 3-state enable bit is set to a 1 by the MCU to program the hardware to 3-state the

serial data output signal for the time slots during the audio frame that are not valid.

The MCU should clear this bit to a 0 to program the hardware to use zero-padding for

the serial data output signal for time slots during the audio frame that are not valid.

5 CSCLKP CSCLK polarity The CSCLK polarity bit is used by the MCU to program the clock edge used for the

CODEC port interface frame sync (CSYNC) output signal, CODEC port interface

serial data output (CDATO) signal and CODEC port interface serial data Input

(CDATI) signal. When this bit is set to a 1, the CSYNC signal will be generated with

the negative edge of the CODEC port interface serial clock (CSCLK) signal. Also,

when this bit is set to a 1, the CDATO signal will be generated with the negative edge

of the CSCLK signal and the CDATI signal will be sampled with the positive edge of

the CSCLK signal. When this bit is cleared to a 0, the CSYNC signal will be

generated with the positive edge of the CSCLK signal. Also, when this bit is cleared

to a 0, the CDATO signal will be generated with the positive edge of the CSCLK

signal and the CDATI signal will be sampled with the negative edge of the CSCLK

signal.

4 CSYNCP CSYNC polarity The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the

CODEC port interface frame sync (CSYNC) output signal to be active high. The

MCU should clear this bit to a 0 to program the polarity of the CSYNC output signal to

be active low.

3 CSYNCL CSYNC length The CSYNC length bit is set to a 1 by the MCU to program the length of the CODEC

port interface frame sync (CSYNC) output signal to be the same number of CSCLK

cycles as time slot 0. The MCU should clear this bit to a 0 to program the length of the

CSYNC output signal to be one CSCLK cycle.

2 BYOR Byte order The byte order bit is used by the MCU to program the byte order for the data moved

by the DMA between the USB endpoint buffer and the CODEC port interface. When

this bit is set to a 1, the byte order of each audio sample will be reversed when the

data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the

byte order of the each audio sample will be unchanged.

1 CSCLKD CSCLK direction The CSCLK direction bit is set to a 1 by the MCU to program the direction of the

CODEC port interface serial clock (CSCLK) signal as an input to the TUSB3200

device. The MCU should clear this bit to a 0 to program the direction of the CSCLK

signal as an output from the TUSB3200 device.

0 CSYNCD CSYNC direction The CSYNC direction bit is set to a 1 by the MCU to program the direction of the

CODEC port interface frame sync (CSYNC) signal as an input to the TUSB3200

device. The MCU should clear this bit to a 0 to program the direction of the CSYNC

signal as an output from the TUSB3200 device.

A–32

A.5.4.4 CODEC Port Interface Configuration Register 4 (CPTCNF4 – Address FFDDh)

The CODEC port interface configuration register 4 is used to store various control bits for the CODEC port interface

operation.

Bit 7 6 5 4 3 2 1 0

Mnemonic ATSL3 ATSL2 ATSL1 ATSL0 CLKS DIVB2 DIVB1 DIVB0

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:4 ATSL(3:0) Command/status address/data

time slot

The command/status address/data time slot bits are set by the MCU to program the

time slots to be used for the secondary communication address and data values. For

the AC ’97 modes of operation, this value should be set to 0001b which will result in

time slot 1 being used for the address and time slot 2 being used for the data. For the

AIC and general-purpose modes of operation, the same time slot is used for both

address and data. For the AIC mode of operation, for example, this value should be

set to 0111b which will result in time slot 7 being used for both the address and data.

0000b = time slot 0, 0001b = time slot 1, …, 1111b = time slot 15

3 CLKS Clock select The clock select bit is used by the MCU to select the source of the clock signal to be

used for the divide by B circuit. The MCU sets this bit to a 1 to select the output of the

divide by I circuit as the clock for the divide by B circuit. The MCU sets this bit to a 0 to

select the output of the divide by M circuit as the clock for the divide by B circuit.

2:0 DIVB(2:0) Divide by B value The divide by B control bits are set by the MCU to program the CSCLK signal divider.

000b = disabled

001b = divide by 2

010b = divide by 3

011b = divide by 4

100b = divide by 5

101b = divide by 6

110b = divide by 7

111b = divide by 8

A–33

A.5.4.5 CODEC Port Interface Control and Status Register (CPTCTL – Address FFDCh)

The CODEC port interface control and status register contains various control and status bits used for the CODEC

port interface operation.

Bit 7 6 5 4 3 2 1 0

Mnemonic RXF RXIE TXE TXIE — CID1 CID0 CRST

Type R R/W R R/W R R/W R/W R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 RXF Receive data register full The receive data register full bit is set to a 1 by hardware when a new data value has

been received into the receive data register from the CODEC device. This bit is read

only and is cleared to a 0 by hardware when the MCU reads the new value from the

receive data register. Note that when the MCU writes to the interrupt vector register,

the CODEC port interface receive data register full interrupt will be cleared but this

status bit will not be cleared at that time.

6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the C-port receive

data register full interrupt.

5 TXE Transmit data register empty The transmit data register empty bit is set to a 1 by hardware when the data value in

the transmit data register has been sent to the CODEC device. This bit is read only

and is cleared to a 0 by hardware when a new data byte is written to the transmit data

the CODEC port interface transmit data register empty interrupt will be cleared but

this status bit will not be cleared at that time.

4 TXIE Transmit interrupt enable The transmit interrupt enable bit is set to a 1 by the MCU to enable the CODEC port

interface transmit data register empty interrupt.

3 — Reserved Reserved for future use.

2:1 CID(1:0) CODEC ID The CODEC ID bits are used by the MCU to select between the primary CODEC

device and the secondary CODEC device for secondary communication in the AC

’97 modes of operation. When the bits are cleared to 00, the primary CODEC device

is selected. When the bits are set to 01, 10 or 11, the secondary CODEC device is

selected. Note that when only a primary CODEC device is connected to the

TUSB3200, the bits should remain cleared to 00.

0 CRST CODEC reset The CODEC reset bit is used by the MCU to control the CODEC port interface reset

(CRESET

) output signal from the TUSB3200 device. When this bit is set to a 1, the

CRESET

signal is a high. When this bit is cleared to a 0, the CRESET signal is active

low. At power up this bit is cleared to a 0, which means the CRESET

output signal will

be active low and will remain active low until the MCU sets this bit to a 1. Note that

this output signal is not used in the I

S modes of operation.

Part #	TUSB3200ACPAH
Description	USB STREAMING CONTROLLER
Category	IC
Availability	Out of Stock
Qty	0

TUSB3200ACPAH

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Technical Document