A–23
A.5.2.6 DMA Channel 2 Control Register (DMATCTL2 – Address FFF4h)
The DMA channel 2 control register is used to store various control bits for DMA channel 2.
Bit 7 6 5 4 3 2 1 0
Mnemonic DMAEN WABEN — — EPDIR EPNUM2 EPNUM1 EPNUM0
Type R/W R/W R R R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7 DMAEN DMA enable The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before
enabling the DMA channel, all other DMA channel configuration bits should be set to
the desired value.
6 WABEN Wrap-around buffer enable The wrap-around buffer enable bit is used by the MCU to enable or disable the
wrap-around buffer operation. The wrap-around buffer operation can only be used
by isochronous out endpoints or isochronous in endpoints that are serviced by the
DMA channels. The wrap-around buffer operation is enabled or disabled separately
for each DMA channel. For a DMA channel, the MCU should set this bit to a 1 to
enable the wrap-around buffer operation and clear this bit to a 0 to disable the
wrap-around buffer operation. Both the DMA channel and UBM logic use this bit to
determine the required functionality.
5 — Reserved Reserved for future use
4 — Reserved Reserved for future use
3 EPDIR USB endpoint direction The USB endpoint direction bit controls the direction of data transfer by this DMA
channel. The MCU should set this bit to a 1 to configure this DMA channel to be used
for a USB in endpoint. The MCU should clear this bit to a 0 to configure this DMA
channel to be used for a USB out endpoint.
2:0 EPNUM(2:0) USB endpoint number The USB endpoint number bits are set by the MCU to define the USB endpoint
number supported by this DMA channel. Keep in mind that endpoint 0 is always
used for the control endpoint, which is serviced by the MCU and not a DMA channel.
001b = Endpoint 1, 010b = Endpoint 2, …, 111b = Endpoint 7
A.5.2.7 DMA Channel 1 Time Slot Assignment Register (Low Byte) (DMATSL1 – Address FFF0h)
The DMA channel 1 time slot assignment register (low byte) contains the eight least significant time slot bits. The time
slot assignment bits are used to define which CODEC port interface time slots are supported by DMA channel 1. The
DMA channel will control the transfer of data between the USB endpoint buffers and the CODEC port interface
registers based on which bits are set. The direction of the data transfer depends on the value of the USB endpoint
direction bit (EPDIR) in the DMA channel 1 control register. The desired time slot bits should be set by the MCU before
the DMA channel is enabled. There are a total of fourteen time slot bits for each DMA channel.
Bit 7 6 5 4 3 2 1 0
Mnemonic TSL7 TSL6 TSL5 TSL4 TSL3 TSL2 TSL1 TSL0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 TSL(7:0) Time slot assignment The DMA time slot assignment bits are set to a 1 by the MCU to define the CODEC
port interface time slots supported by this DMA channel.
